[PATCH 0/3] Get cache information from userland
Zong Li
zong.li at sifive.com
Sun Jul 26 23:03:09 EDT 2020
On Fri, Jul 3, 2020 at 4:57 PM Zong Li <zong.li at sifive.com> wrote:
>
> There are no standard CSR registers to provide cache information, the
> way for RISC-V is to get this information from DT. Currently, AT_L1I_X,
> AT_L1D_X and AT_L2_X are present in glibc header, and sysconf syscall
> could use them to get information of cache through AUX vector. We
> exploit 'struct cacheinfo' to obtain the information of cache, then we
> don't need additional variable or data structure to record it.
>
> We also need some works in glibc, but we have to support the function in
> kernel first by rule of glibc, then post the patch to glibc site.
>
> The result of 'getconf -a' as follows:
>
> LEVEL1_ICACHE_SIZE 32768
> LEVEL1_ICACHE_ASSOC 8
> LEVEL1_ICACHE_LINESIZE 64
> LEVEL1_DCACHE_SIZE 32768
> LEVEL1_DCACHE_ASSOC 8
> LEVEL1_DCACHE_LINESIZE 64
> LEVEL2_CACHE_SIZE 2097152
> LEVEL2_CACHE_ASSOC 32
> LEVEL2_CACHE_LINESIZE 64
>
> Zong Li (3):
> riscv: Set more data to cacheinfo
> riscv: Define AT_VECTOR_SIZE_ARCH for ARCH_DLINFO
> riscv: Add cache information in AUX vector
>
> arch/riscv/include/asm/cacheinfo.h | 14 +++++
> arch/riscv/include/asm/elf.h | 13 ++++
> arch/riscv/include/uapi/asm/auxvec.h | 24 ++++++++
> arch/riscv/kernel/cacheinfo.c | 92 +++++++++++++++++++++++-----
> 4 files changed, 127 insertions(+), 16 deletions(-)
> create mode 100644 arch/riscv/include/asm/cacheinfo.h
>
> --
> 2.27.0
>
ping
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