[PATCH v2 5/5] dt-bindings: timer: Add CLINT bindings
robh at kernel.org
Tue Jul 14 11:04:12 EDT 2020
On Mon, Jul 13, 2020 at 9:47 PM Anup Patel <anup at brainfault.org> wrote:
> On Tue, Jul 14, 2020 at 8:07 AM Rob Herring <robh at kernel.org> wrote:
> > On Sat, Jun 27, 2020 at 09:49:57PM +0530, Anup Patel wrote:
> > > We add DT bindings documentation for CLINT device.
> > >
> > > Signed-off-by: Anup Patel <anup.patel at wdc.com>
> > > Reviewed-by: Palmer Dabbelt <palmerdabbelt at google.com>
> > > ---
> > > .../bindings/timer/sifive,clint.txt | 34 +++++++++++++++++++
> > > 1 file changed, 34 insertions(+)
> > > create mode 100644 Documentation/devicetree/bindings/timer/sifive,clint.txt
> > Bindings should be in DT schema format now.
> Okay, will update.
> > >
> > > diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.txt b/Documentation/devicetree/bindings/timer/sifive,clint.txt
> > > new file mode 100644
> > > index 000000000000..45b75347a7d5
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/timer/sifive,clint.txt
> > > @@ -0,0 +1,34 @@
> > > +SiFive Core Local Interruptor (CLINT)
> > > +-------------------------------------
> > > +
> > > +SiFive (and other RISC-V) SOCs include an implementation of the SiFive Core
> > > +Local Interruptor (CLINT) for M-mode timer and inter-processor interrupts.
> > > +
> > > +It directly connects to the timer and inter-processor interrupt lines of
> > > +various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local interrupt
> > > +controller is the parent interrupt controller for CLINT device.
> > > +
> > > +The clock frequency of CLINT is specified via "timebase-frequency" DT
> > > +property of "/cpus" DT node. The "timebase-frequency" DT property is
> > > +described in: Documentation/devicetree/bindings/riscv/cpus.yaml
> > > +
> > > +Required properties:
> > > +- compatible : should be "riscv,clint0" or "sifive,clint-1.0.0". A specific
> > A new versioning scheme from SiFive? To review, we don't do version
> > numbers unless there's a well defined and documented scheme. IOW, one
> > that's not s/w folks just making up v1, v2, v3, etc.
> The "riscv,clint0" is already used by various RISC-V systems (including QEMU).
Not my problem that undocumented bindings are being used.
> The "sifive,clint-1.0.0" is for being consistent with the PLIC
> versioning scheme.
Where is that documented? This is what I expect you to be following or
updating to match:
> There is no clear documentation of CLINT versioning scheme. I think it's best
> to just drop "sifive,clint-1.0.0" . Agree ??
No, because then you are left with a very generic compatible string.
You need something specific enough to handle any implementation
features/quirks/bugs without needing a DT update. Typically, this
means a per SoC compatible string for a block as even the same IP
version can have different integration quirks.
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