[PATCH 1/2] riscv: Fix building error in entry.S when CONFIG_RISCV_M_MODE is enabled

Greentime Hu greentime.hu at sifive.com
Mon Jul 13 04:32:15 EDT 2020

arch/riscv/kernel/entry.S: Assembler messages:
arch/riscv/kernel/entry.S:106: Error: illegal operands `andi a0,s1,0x00001800'

This building error is because of the SR_MPP value is too large to be used
as an immediate value for andi. To fix this issue I use li to set the
immediate value to t0, then it can use t0 and s1 to do and operation.

Reported-by: kernel test robot <lkp at intel.com>
Signed-off-by: Greentime Hu <greentime.hu at sifive.com>
 arch/riscv/kernel/entry.S | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S
index 6ed579fc1073..000984695cd6 100644
--- a/arch/riscv/kernel/entry.S
+++ b/arch/riscv/kernel/entry.S
@@ -99,7 +99,8 @@ _save_context:
 	/* If previous state is in user mode, call context_tracking_user_exit. */
-	andi a0, s1, SR_SPP
+	li t0, SR_PP
+	and a0, s1, t0
 	bnez a0, skip_context_tracking
 	call context_tracking_user_exit

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