[PATCH] riscv: add NT_RISCV_CSR constant

Andrew Burgess andrew.burgess at embecosm.com
Mon Dec 14 10:24:37 EST 2020

I am currently working on adding support to GDB for dumping bare metal
core files for RISC-V.  As part of this work I would like to include
support for dumping RISC-V CSRs.

The format of these bare metal core files is planned to be ELF + NOTES
very similar to the core file format use by Linux.

As such I need to pick a number to use for the CSR note.  Currently
Linux for RISC-V doesn't support writing out CSRs, and so no number
has been assigned for a CSR note.

In this patch I propose reserving a note number for RISC-V CSRs.  This
note isn't currently used within Linux, but might be one day.  Given
how the per-architecture notes are allocated this patch not only
reserves a note number for the CSRs, but as the first RISC-V specific
note number, it reserves the whole 0x9?? number range for RISC-V
specific notes.

Reserving this constant now will allow for coordination between Linux
and user-space tools that work with core files (like GDB) without
risking possible number conflicts in the future.

I don't know if it's acceptable to have reserved, but otherwise
unused, constants like this in the kernel or not.
 include/uapi/linux/elf.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/uapi/linux/elf.h b/include/uapi/linux/elf.h
index 34c02e4290fe..7db3752108c8 100644
--- a/include/uapi/linux/elf.h
+++ b/include/uapi/linux/elf.h
@@ -428,6 +428,7 @@ typedef struct elf64_shdr {
 #define NT_MIPS_DSP	0x800		/* MIPS DSP ASE registers */
 #define NT_MIPS_FP_MODE	0x801		/* MIPS floating-point mode */
 #define NT_MIPS_MSA	0x802		/* MIPS SIMD registers */
+#define NT_RISCV_CSR	0x900		/* RISC-V Control Status Registers */
 /* Note header in a PT_NOTE section */
 typedef struct elf32_note {

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