[RFC PATCH v2 3/4] RISC-V: Initial DTS for Microchip ICICLE board

Atish Patra Atish.Patra at wdc.com
Wed Dec 2 13:49:29 EST 2020


On Wed, 2020-12-02 at 16:20 +0000, Daire.McNamara at microchip.com wrote:
> 
> 
> From: Atish Patra <atish.patra at wdc.com>
> Sent: Friday 13 November 2020 20:25
> To: linux-kernel at vger.kernel.org <linux-kernel at vger.kernel.org>
> Cc: Atish Patra <atish.patra at wdc.com>; Albert Ou < 
> aou at eecs.berkeley.edu>; Alistair Francis <alistair.francis at wdc.com>;
> Anup Patel <anup.patel at wdc.com>; devicetree at vger.kernel.org < 
> devicetree at vger.kernel.org>; linux-riscv at lists.infradead.org < 
> linux-riscv at lists.infradead.org>; Palmer Dabbelt
> <palmer at dabbelt.com>; Paul Walmsley <paul.walmsley at sifive.com>; Rob
> Herring <  robh+dt at kernel.org>; Daire McNamara - X61553 < 
> Daire.McNamara at microchip.com>; Cyril Jean - M31571 < 
> Cyril.Jean at microchip.com>; Ivan Griffin - X61451 < 
> Ivan.Griffin at microchip.com>; Conor Dooley - M52691 < 
> Conor.Dooley at microchip.com>
> Subject: [RFC PATCH v2 3/4] RISC-V: Initial DTS for Microchip ICICLE
> board 
> EXTERNAL EMAIL: Do not click links or open attachments unless you
> know the content is safe
> 
> Add initial DTS for Microchip ICICLE board having only
> essential devcies (clocks, sdhci, ethernet, serial, etc).
> The device tree is based on the U-Boot patch.
> 
>  
> https://patchwork.ozlabs.org/project/uboot/patch/20201110103414.10142-6-padmarao.begari@microchip.com/
> 
> Signed-off-by: Atish Patra <atish.patra at wdc.com>
> ---
>  arch/riscv/boot/dts/Makefile                  |   1 +
>  arch/riscv/boot/dts/microchip/Makefile        |   2 +
>  .../microchip/microchip-mpfs-icicle-kit.dts   |  54 +++
>  .../boot/dts/microchip/microchip-mpfs.dtsi    | 342
> ++++++++++++++++++
>  4 files changed, 399 insertions(+)
>  create mode 100644 arch/riscv/boot/dts/microchip/Makefile
>  create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs-
> icicle-kit.dts
>  create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
> 
> diff --git a/arch/riscv/boot/dts/Makefile
> b/arch/riscv/boot/dts/Makefile
> index ca1f8cbd78c0..3ea94ea0a18a 100644
> --- a/arch/riscv/boot/dts/Makefile
> +++ b/arch/riscv/boot/dts/Makefile
> @@ -1,5 +1,6 @@
>  # SPDX-License-Identifier: GPL-2.0
>  subdir-y += sifive
>  subdir-y += kendryte
> +subdir-y += microchip
> 
>  obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y))
> diff --git a/arch/riscv/boot/dts/microchip/Makefile
> b/arch/riscv/boot/dts/microchip/Makefile
> new file mode 100644
> index 000000000000..622b12771fd3
> --- /dev/null
> +++ b/arch/riscv/boot/dts/microchip/Makefile
> @@ -0,0 +1,2 @@
> +# SPDX-License-Identifier: GPL-2.0
> +dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += microchip-mpfs-icicle-
> kit.dtb
> diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-
> kit.dts b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
> new file mode 100644
> index 000000000000..9a382ab0a799
> --- /dev/null
> +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
> @@ -0,0 +1,54 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/* Copyright (c) 2020 Microchip Technology Inc */
> +
> +/dts-v1/;
> +
> +#include "microchip-mpfs.dtsi"
> +
> +/* Clock frequency (in Hz) of the rtcclk */
> +#define RTCCLK_FREQ            1000000
> +
> +/ {
> +       #address-cells = <2>;
> +       #size-cells = <2>;
> +       model = "Microchip PolarFire-SoC Icicle Kit";
> +       compatible = "microchip,mpfs-icicle-kit",
> "microchip,polarfire-soc";
> +
> +       chosen {
> +               stdout-path = &serial0;
> +       };
> +
> +       cpus {
> +               timebase-frequency = <RTCCLK_FREQ>;
> +       };
> +
> +       memory at 80000000 {
> +               device_type = "memory";
> +               reg = <0x0 0x80000000 0x0 0x40000000>;
> +               clocks = <&clkcfg 26>;
> +       };
> +
> +       soc {
> +       };
> +};
> +
> +&serial0 {
> +       status = "okay";
> +};
> +
> +&serial1 {
> +       status = "okay";
> +};
> +
> +&serial2 {
> +       status = "okay";
> +};
> +
> +&serial3 {
> +       status = "okay";
> +};
> +
> +&sdcard {
> +       status = "okay";
> +};
> +
> diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
> b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
> new file mode 100644
> index 000000000000..63ac60f345d8
> --- /dev/null
> +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
> @@ -0,0 +1,342 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/* Copyright (c) 2020 Microchip Technology Inc */
> +
> +/dts-v1/;
> +
> +/ {
> +       #address-cells = <2>;
> +       #size-cells = <2>;
> +       model = "Microchip PolarFire-SoC";
> +       compatible = "microchip,polarfire-soc";
> +
> +       chosen {
> +       };
> +
> +       cpus {
> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +
> +               cpu at 0 {
> +                       clock-frequency = <0>;
> +                       compatible = "sifive,rocket0", "riscv";
> +                       device_type = "cpu";
> +                       i-cache-block-size = <64>;
> +                       i-cache-sets = <128>;
> +                       i-cache-size = <16384>;
> +                       reg = <0>;
> +                       riscv,isa = "rv64imac";
> +                       status = "disabled";
> +
> +                       cpu0_intc: interrupt-controller {
> +                               #interrupt-cells = <1>;
> +                               compatible = "riscv,cpu-intc";
> +                               interrupt-controller;
> +                       };
> +               };
> +
> +               cpu at 1 {
> +                       clock-frequency = <0>;
> +                       compatible = "sifive,rocket0", "riscv";
> +                       d-cache-block-size = <64>;
> +                       d-cache-sets = <64>;
> +                       d-cache-size = <32768>;
> +                       d-tlb-sets = <1>;
> +                       d-tlb-size = <32>;
> +                       device_type = "cpu";
> +                       i-cache-block-size = <64>;
> +                       i-cache-sets = <64>;
> +                       i-cache-size = <32768>;
> +                       i-tlb-sets = <1>;
> +                       i-tlb-size = <32>;
> +                       mmu-type = "riscv,sv39";
> +                       reg = <1>;
> +                       riscv,isa = "rv64imafdc";
> +                       tlb-split;
> +                       status = "okay";
> +
> +                       cpu1_intc: interrupt-controller {
> +                               #interrupt-cells = <1>;
> +                               compatible = "riscv,cpu-intc";
> +                               interrupt-controller;
> +                       };
> +               };
> +
> +               cpu at 2 {
> +                       clock-frequency = <0>;
> +                       compatible = "sifive,rocket0", "riscv";
> +                       d-cache-block-size = <64>;
> +                       d-cache-sets = <64>;
> +                       d-cache-size = <32768>;
> +                       d-tlb-sets = <1>;
> +                       d-tlb-size = <32>;
> +                       device_type = "cpu";
> +                       i-cache-block-size = <64>;
> +                       i-cache-sets = <64>;
> +                       i-cache-size = <32768>;
> +                       i-tlb-sets = <1>;
> +                       i-tlb-size = <32>;
> +                       mmu-type = "riscv,sv39";
> +                       reg = <2>;
> +                       riscv,isa = "rv64imafdc";
> +                       tlb-split;
> +                       status = "okay";
> +
> +                       cpu2_intc: interrupt-controller {
> +                               #interrupt-cells = <1>;
> +                               compatible = "riscv,cpu-intc";
> +                               interrupt-controller;
> +                       };
> +               };
> +
> +               cpu at 3 {
> +                       clock-frequency = <0>;
> +                       compatible = "sifive,rocket0", "riscv";
> +                       d-cache-block-size = <64>;
> +                       d-cache-sets = <64>;
> +                       d-cache-size = <32768>;
> +                       d-tlb-sets = <1>;
> +                       d-tlb-size = <32>;
> +                       device_type = "cpu";
> +                       i-cache-block-size = <64>;
> +                       i-cache-sets = <64>;
> +                       i-cache-size = <32768>;
> +                       i-tlb-sets = <1>;
> +                       i-tlb-size = <32>;
> +                       mmu-type = "riscv,sv39";
> +                       reg = <3>;
> +                       riscv,isa = "rv64imafdc";
> +                       tlb-split;
> +                       status = "okay";
> +
> +                       cpu3_intc: interrupt-controller {
> +                               #interrupt-cells = <1>;
> +                               compatible = "riscv,cpu-intc";
> +                               interrupt-controller;
> +                       };
> +               };
> +
> +               cpu at 4 {
> +                       clock-frequency = <0>;
> +                       compatible = "sifive,rocket0", "riscv";
> +                       d-cache-block-size = <64>;
> +                       d-cache-sets = <64>;
> +                       d-cache-size = <32768>;
> +                       d-tlb-sets = <1>;
> +                       d-tlb-size = <32>;
> +                       device_type = "cpu";
> +                       i-cache-block-size = <64>;
> +                       i-cache-sets = <64>;
> +                       i-cache-size = <32768>;
> +                       i-tlb-sets = <1>;
> +                       i-tlb-size = <32>;
> +                       mmu-type = "riscv,sv39";
> +                       reg = <4>;
> +                       riscv,isa = "rv64imafdc";
> +                       tlb-split;
> +                       status = "okay";
> +                       cpu4_intc: interrupt-controller {
> +                               #interrupt-cells = <1>;
> +                               compatible = "riscv,cpu-intc";
> +                               interrupt-controller;
> +                       };
> +               };
> +       };
> +
> +       soc {
> +               #address-cells = <2>;
> +               #size-cells = <2>;
> +               compatible = "simple-bus";
> +               ranges;
> +
> +               cache-controller at 2010000 {
> +                       compatible = "sifive,fu540-c000-ccache",
> "cache";
> +                       cache-block-size = <64>;
> +                       cache-level = <2>;
> +                       cache-sets = <1024>;
> +                       cache-size = <2097152>;
> +                       cache-unified;
> +                       interrupt-parent = <&plic>;
> +                       interrupts = <1 2 3>;
> +                       reg = <0x0 0x2010000 0x0 0x1000>;
> +               };
> +
> +               clint at 2000000 {
> +                       compatible = "riscv,clint0";
> +                       reg = <0x0 0x2000000 0x0 0xC000>;
> +                       interrupts-extended = <&cpu0_intc 3
> &cpu0_intc 7
> +                                               &cpu1_intc 3
> &cpu1_intc 7
> +                                               &cpu2_intc 3
> &cpu2_intc 7
> +                                               &cpu3_intc 3
> &cpu3_intc 7
> +                                               &cpu4_intc 3
> &cpu4_intc 7>;
> +               };
> +
> +               plic: interrupt-controller at c000000 {
> +                       #interrupt-cells = <1>;
> +                       compatible = "sifive,plic-1.0.0";
> +                       reg = <0x0 0xc000000 0x0 0x4000000>;
> +                       riscv,ndev = <53>;
> Hi Atish, can you change this from 53 to 186, please?
> riscv,ndev = <186>;

Thanks for catching it. Done.

> +                       interrupt-controller;
> +                       interrupts-extended = <&cpu0_intc 11
> +                                       &cpu1_intc 11 &cpu1_intc 9
> +                                       &cpu2_intc 11 &cpu2_intc 9
> +                                       &cpu3_intc 11 &cpu3_intc 9
> +                                       &cpu4_intc 11 &cpu4_intc 9>;
> +               };
> +
> +               dma at 3000000 {
> +                       compatible = "sifive,fu540-c000-pdma";
> +                       reg = <0x0 0x3000000 0x0 0x8000>;
> +                       interrupt-parent = <&plic>;
> +                       interrupts = <23 24 25 26 27 28 29 30>;
> +                       #dma-cells = <1>;
> +               };
> +
> +               refclk: refclk {
> +                       compatible = "fixed-clock";
> +                       #clock-cells = <0>;
> +                       clock-frequency = <600000000>;
> +                       clock-output-names = "msspllclk";
> +               };
> +
> +               clkcfg: clkcfg at 20002000 {
> +                       compatible = "microchip,pfsoc-clkcfg";
> +                       reg = <0x0 0x20002000 0x0 0x1000>;
> +                       reg-names = "mss_sysreg";
> +                       clocks = <&refclk>;
> +                       #clock-cells = <1>;
> +                       clock-output-names = "cpuclk", "axiclk",
> "ahbclk", "ENVMclk",   /* 0-3   */
> +                                "MAC0clk", "MAC1clk", "MMCclk",
> "TIMERclk",            /* 4-7   */
> +                               "MMUART0clk", "MMUART1clk",
> "MMUART2clk", "MMUART3clk", /* 8-11  */
> +                               "MMUART4clk", "SPI0clk", "SPI1clk",
> "I2C0clk",          /* 12-15 */
> +                               "I2C1clk", "CAN0clk", "CAN1clk",
> "USBclk",              /* 16-19 */
> +                               "RESERVED", "RTCclk", "QSPIclk",
> "GPIO0clk",            /* 20-23 */
> +                               "GPIO1clk", "GPIO2clk", "DDRCclk",
> "FIC0clk",           /* 24-27 */
> +                               "FIC1clk", "FIC2clk", "FIC3clk",
> "ATHENAclk", "CFMclk"; /* 28-32 */
> Can we shorten clock names to:
>                        clock-output-names = "cpu", "axi", "ahb",
> "envm",
>                                 "mac0", "mac1", "mmc", "timer",
>                                "mmuart0", "mmuart1", "mmuart2",
> "mmuart3",
>                                "mmuart4", "spi0", "spi1", "i2c0",
>                                "i2c1", "can0", "can1", "usb",
>                                "rsvd", "rtc", "qspi", "gpio0",
>                                "gpio1", "gpio2", "ddrc", "fic0",
>                                "fic1", "fic2", "fic3", "athena",
> "cfm";
> +               };

Sure. I will update that in v3.

> +
> +               serial0: serial at 20000000 {
> +                       compatible = "ns16550a";
> +                       reg = <0x0 0x20000000 0x0 0x400>;
> +                       reg-io-width = <4>;
> +                       reg-shift = <2>;
> +                       interrupt-parent = <&plic>;
> +                       interrupts = <90>;
> +                       current-speed = <115200>;
> +                       clocks = <&clkcfg 8>;
> +                       status = "disabled";
> +               };
> +
> +               serial1: serial at 20100000 {
> +                       compatible = "ns16550a";
> +                       reg = <0x0 0x20100000 0x0 0x400>;
> +                       reg-io-width = <4>;
> +                       reg-shift = <2>;
> +                       interrupt-parent = <&plic>;
> +                       interrupts = <91>;
> +                       current-speed = <115200>;
> +                       clocks = <&clkcfg 9>;
> +                       status = "disabled";
> +               };
> +
> +               serial2: serial at 20102000 {
> +                       compatible = "ns16550a";
> +                       reg = <0x0 0x20102000 0x0 0x400>;
> +                       reg-io-width = <4>;
> +                       reg-shift = <2>;
> +                       interrupt-parent = <&plic>;
> +                       interrupts = <92>;
> +                       current-speed = <115200>;
> +                       clocks = <&clkcfg 10>;
> +                       status = "disabled";
> +               };
> +
> +               serial3: serial at 20104000 {
> +                       compatible = "ns16550a";
> +                       reg = <0x0 0x20104000 0x0 0x400>;
> +                       reg-io-width = <4>;
> +                       reg-shift = <2>;
> +                       interrupt-parent = <&plic>;
> +                       interrupts = <93>;
> +                       current-speed = <115200>;
> +                       clocks = <&clkcfg 11>;
> +                       status = "disabled";
> +               };
> +
> +               emmc: mmc at 20008000 {
> +                       compatible = "cdns,sd4hc";
> +                       reg = <0x0 0x20008000 0x0 0x1000>;
> +                       interrupt-parent = <&plic>;
> +                       interrupts = <88 89>;
> +                       pinctrl-names = "default";
> +                       clocks = <&clkcfg 6>;
> +                       bus-width = <4>;
> +                       cap-mmc-highspeed;
> +                       mmc-ddr-3_3v;
> +                       max-frequency = <200000000>;
> +                       non-removable;
> +                       no-sd;
> +                       no-sdio;
> +                       voltage-ranges = <3300 3300>;
> +                       status = "disabled";
> +               };
> +
> +               sdcard: sdhc at 20008000 {
> +                       compatible = "cdns,sd4hc";
> +                       reg = <0x0 0x20008000 0x0 0x1000>;
> +                       interrupt-parent = <&plic>;
> +                       interrupts = <88>;
> +                       pinctrl-names = "default";
> +                       clocks = <&clkcfg 6>;
> +                       bus-width = <4>;
> +                       disable-wp;
> +                       no-1-8-v;
> +                       cap-mmc-highspeed;
> +                       cap-sd-highspeed;
> +                       card-detect-delay = <200>;
> +                       sd-uhs-sdr12;
> +                       sd-uhs-sdr25;
> +                       sd-uhs-sdr50;
> +                       sd-uhs-sdr104;
> +                       max-frequency = <200000000>;
> +                       status = "disabled";
> +               };
> +
> +               emac0: ethernet at 20110000 {
> +                       compatible = "cdns,macb";
> +                       reg = <0x0 0x20110000 0x0 0x2000>;
> +                       interrupt-parent = <&plic>;
> +                       interrupts = <64 65 66 67>;
> +                       local-mac-address = [00 00 00 00 00 00];
> +                       phy-mode = "sgmii";
> +                       clocks = <&clkcfg 5>, <&clkcfg 2>;
> +                       clock-names = "pclk", "hclk";
> +                       status = "disabled";
> +
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +                       phy-handle = <&phy0>;
> +                       phy0: ethernet-phy at 8 {
> +                               reg = <8>;
> +                               ti,fifo-depth = <0x01>;
> +                       };
> +               };
> +
> +               emac1: ethernet at 20112000 {
> +                       compatible = "cdns,macb";
> +                       reg = <0x0 0x20112000 0x0 0x2000>;
> +                       interrupt-parent = <&plic>;
> +                       interrupts = <70 71 72 73>;
> +                       mac-address = [00 00 00 00 00 00];
> +                       phy-mode = "sgmii";
> +                       clocks = <&clkcfg 5>, <&clkcfg 2>;
> +                       clock-names = "pclk", "hclk";
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +                       phy1: ethernet-phy at 9 {
> +                               reg = <9>;
> +                               ti,fifo-depth = <0x01>;
> +                       };
> +               };
> +
> +       };
> +};
> --
> 2.25.1
> 

-- 
Regards,
Atish


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