[PATCH v4 0/3] Get cache information from userland
zong.li at sifive.com
Mon Aug 31 03:33:47 EDT 2020
There are no standard CSR registers to provide cache information, the
way for RISC-V is to get this information from DT. Currently, AT_L1I_X,
AT_L1D_X and AT_L2_X are present in glibc header, and sysconf syscall
could use them to get information of cache through AUX vector. We
exploit 'struct cacheinfo' to obtain the information of cache, then we
don't need additional variable or data structure to record it.
We also need some works in glibc, but we have to support the function in
kernel first by rule of glibc, then post the patch to glibc site.
The result of 'getconf -a' as follows:
Changed in v4:
- Check null pointer before use.
- Re-write the code for readability.
- Rebase source to v5.9-rc3.
Changed in v3:
- Fix sparse warning: Use NULL instead of integer 0.
Changed in v2:
- Add error checking for parsing cache properties.
Zong Li (3):
riscv: Set more data to cacheinfo
riscv: Define AT_VECTOR_SIZE_ARCH for ARCH_DLINFO
riscv: Add cache information in AUX vector
arch/riscv/include/asm/cacheinfo.h | 5 ++
arch/riscv/include/asm/elf.h | 13 ++++
arch/riscv/include/uapi/asm/auxvec.h | 24 +++++++
arch/riscv/kernel/cacheinfo.c | 98 +++++++++++++++++++++++-----
4 files changed, 124 insertions(+), 16 deletions(-)
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