[PATCH 01/10] usb: dwc3: add an option to adjust the dwc3 global register start offset

[stanley_chang]

In general, the dwc3 usb controller designs the global register start offset
at 0xc100. The dwc3 global register start offset of Realtek SoC is at 0x8100.
Therefore, we add a property to adjust this offset in dts.

Signed-off-by: stanley_chang <stanley_chang at realtek.com>
---
 drivers/usb/dwc3/core.c | 13 +++++++++++++
 drivers/usb/dwc3/core.h |  5 ++++-
 2 files changed, 17 insertions(+), 1 deletion(-)

diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index f561c6c9e8a9..e842e926b535 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -1464,6 +1464,19 @@ static int dwc3_probe(struct platform_device *pdev)
 	dwc_res = *res;
 	dwc_res.start += DWC3_GLOBALS_REGS_START;
 
+	/* For some dwc3 controller, the dwc3 global register start address is
+	 * not at DWC3_GLOBALS_REGS_START (0xc100).
+	 */
+	device_property_read_u32(dev, "snps,fixed_dwc3_globals_regs_start",
+				 &dwc->fixed_dwc3_globals_regs_start);
+	if (dwc->fixed_dwc3_globals_regs_start) {
+		dwc_res.start -= DWC3_GLOBALS_REGS_START;
+		dwc_res.start += dwc->fixed_dwc3_globals_regs_start;
+		dev_info(dev,
+		    "fixed dwc3 globals register start address from 0x%llx to end 0x%llx\n",
+		    dwc_res.start, dwc_res.end);
+	}
+
 	regs = devm_ioremap_resource(dev, &dwc_res);
 	if (IS_ERR(regs))
 		return PTR_ERR(regs);
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 1c8b349379af..6b9eb777085f 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -1031,7 +1031,8 @@ struct dwc3_scratchpad_array {
  * @dis_metastability_quirk: set to disable metastability quirk.
  * @imod_interval: set the interrupt moderation interval in 250ns
  *                 increments or 0 to disable.
- */
+ * @fixed_dwc3_globals_regs_start: fix the dwc3 global register start address.
+*/
 struct dwc3 {
 	struct work_struct	drd_work;
 	struct dwc3_trb		*ep0_trb;
@@ -1220,6 +1221,8 @@ struct dwc3 {
 	unsigned		dis_metastability_quirk:1;
 
 	u16			imod_interval;
+
+	u32			fixed_dwc3_globals_regs_start;
 };
 
 #define INCRX_BURST_MODE 0
-- 
2.28.0