[PATCH v2 2/5] dt-bindings: PCI: qcom,shikra-pcie: Document the Shikra PCIe Controller

[Sushrut Shree Trivedi]

On 9/1/2026 2:12 PM, Krzysztof Kozlowski wrote:
> On Mon, Aug 31, 2026 at 12:56:02PM +0530, Sushrut Shree Trivedi wrote:
>> Add a dedicated schema for the PCIe controller found on the Shikra
>> platform.
>>
>> Shikra controller supports upto PCIe Gen3 but the PHY is
>> only capable of Gen2, hence the max link speed  is limited
>> to Gen2 to avoid link-up failures.
>>
>> Signed-off-by: Sushrut Shree Trivedi <sushrut.trivedi at oss.qualcomm.com>
>> ---
>>   .../devicetree/bindings/pci/qcom,shikra-pcie.yaml  | 218 +++++++++++++++++++++
>>   1 file changed, 218 insertions(+)
>>
> What is the difference in the binding against Eliza? IOW, why does this
> need a separate file unlike Eliza?
Shikra does not have the Config NoC AXI clock unlike sm8550 / eliza. Apart
from that, minItems for reg  and interrupts need to be updated. I actually
didn't see any bindings with a clock constraint added for only a single 
compatible.

Do you suggest constraining shikra clock-names and other properties 
under an if
block inside sm8550 binding itself ?
>
> ...
>
>> +            reset-names = "pci";
>> +
>> +            power-domains = <&gcc GCC_PCIE_GDSC>;
>> +
>> +            max-link-speed = <2>;
>> +
>> +            operating-points-v2 = <&pcie_opp_table>;
>> +
>> +            pcie_opp_table: opp-table {
>> +                    compatible = "operating-points-v2";
> Are you sure dt-check-style does not complain?
ACK'd
>
>> +
>> +                    /* GEN 1 x1 */
>> +                    opp-2500000 {
>> +                            opp-hz = /bits/ 64 <2500000>;
>> +                            required-opps = <&rpmpd_opp_low_svs>;
>> +                            opp-peak-kBps = <250000 1>;
>> +                            opp-level = <1>;
>> +                    };
>> +
> Best regards,
> Krzysztof