[PATCH v4 1/6] dt-bindings: phy: qcom: add Nord QMP PCIe PHY binding

[sashiko-bot at kernel.org]

> Document the PCIe PHY found on the Qualcomm Nord platform.
> 
> Nord has a 32.0 GT/s capable QMP PCIe PHY that can operate in multiple
> lane configurations using four PHY segments (A/B/C/D). The active
> topology is selected by firmware through a TCSR configuration
> register and may be configured as x16, x8+x8, x8+x4+x4, or
> x8+x4+x2+x2.
> 
> The binding describes the register regions, clocks, resets, power
> domains, regulators, PHY provider interface, clock provider interface,
> and the qcom,link-mode property used by the driver to discover the
> active lane configuration programmed by firmware.
> 
> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru at oss.qualcomm.com>

Sashiko has reviewed this patch and found no issues. It looks great!

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260921-nord-v4-0-ed05c6e09240@oss.qualcomm.com?part=1