[PATCH RFC v3 11/12] arm64: dts: s32g: Add PCIe controller nodes

[sashiko-bot at kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] pcie: dt-bindings: invalid 32-bit space code for 64-bit PCI window
--

commit 584612463291c6e4c640175e9ad62d085a5e585d
Author: Jan Petrous (OSS) <jan.petrous at oss.nxp.com>

arm64: dts: s32g: Add PCIe controller nodes

This commit adds the disabled PCIe controller nodes (pcie0 and pcie1)
for the S32G2 and S32G3 SoCs. It includes register mappings, interrupts,
and the ranges properties for mapping PCI addresses to CPU memory.

> diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> index 404913b208fb8..539840340318d 100644
> --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
[ ... ]
> @@ -918,7 +918,88 @@ gic: interrupt-controller at 50800000 {
[ ... ]
> +	pcie0: pcie at 40400000 {
> +		compatible = "nxp,s32g2-pcie";
> +		reg = <0x00 0x40400000 0x0 0x00001000>,	/* dbi */
[ ... ]
> +		ranges = <0x01000000 0x0 0x00000000 0x5f 0xfffe0000 0x0 0x00010000>,
> +			 <0x02000000 0x0 0x00000000 0x58 0x00000000 0x0 0x80000000>,
> +			 <0x02000000 0x1 0x00000000 0x59 0x00000000 0x6 0xfffe0000>;

[Severity: Medium]
Does this ranges property use an incorrect 32-bit space code for a 64-bit PCI
window?

The third entry maps a 64-bit PCI address (0x1 0x00000000) and a size over 4GB
(0x6 0xfffe0000), but starts with the 32-bit memory space code (0x02000000).

According to Open Firmware PCI bindings, regions with addresses or sizes
exceeding 32 bits should use the 64-bit memory space code (0x03000000 for
non-prefetchable or 0x43000000 for prefetchable).

Could this cause device tree parsers in the kernel or U-Boot to reject the
mapping or truncate the address, potentially leading to functional failures for
devices needing memory in this range?

[ ... ]
> +	pcie1: pcie at 44100000 {
> +		compatible = "nxp,s32g2-pcie";
> +		reg = <0x00 0x44100000 0x0 0x00001000>,	/* dbi */
[ ... ]
> +		ranges = <0x01000000 0x0 0x00000000 0x4f 0xfffe0000 0x0 0x00010000>,
> +			 <0x02000000 0x0 0x00000000 0x48 0x00000000 0x0 0x80000000>,
> +			 <0x02000000 0x1 0x00000000 0x49 0x00000000 0x6 0xfffe0000>;

[Severity: Medium]
Is this code also using a 32-bit memory space code (0x02000000) for a 64-bit
PCI window?

> diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi
> index 0d001b2895c61..fdf086363c020 100644
> --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi
[ ... ]
> @@ -1069,6 +1070,86 @@ gic: interrupt-controller at 50800000 {
[ ... ]
> +	pcie0: pcie at 40400000 {
> +		compatible = "nxp,s32g3-pcie", "nxp,s32g2-pcie";
> +		reg = <0x00 0x40400000 0x0 0x00001000>,	/* dbi */
[ ... ]
> +		ranges = <0x01000000 0x0 0x00000000 0x5f 0xfffe0000 0x0 0x00010000>,
> +			 <0x02000000 0x0 0x00000000 0x58 0x00000000 0x0 0x80000000>,
> +			 <0x02000000 0x1 0x00000000 0x59 0x00000000 0x6 0xfffe0000>;

[Severity: Medium]
Is this code also using a 32-bit memory space code (0x02000000) for a 64-bit
PCI window?

[ ... ]
> +	pcie1: pcie at 44100000 {
> +		compatible = "nxp,s32g3-pcie", "nxp,s32g2-pcie";
> +		reg = <0x00 0x44100000 0x0 0x00001000>,	/* dbi */
[ ... ]
> +		ranges = <0x01000000 0x0 0x00000000 0x4f 0xfffe0000 0x0 0x00010000>,
> +			 <0x02000000 0x0 0x00000000 0x48 0x00000000 0x0 0x80000000>,
> +			 <0x02000000 0x1 0x00000000 0x49 0x00000000 0x6 0xfffe0000>;

[Severity: Medium]
Is this code also using a 32-bit memory space code (0x02000000) for a 64-bit
PCI window?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260919-s32g_serdes-v3-0-9d68868c1e89@oss.nxp.com?part=11