[PATCH RFC v3 05/12] net: pcs: Add NXP S32G XPCS driver

[sashiko-bot at kernel.org]

> From: Vincent Guittot <vincent.guittot at linaro.org>
> 
> The S32G SoC family includes two SerDes subsystems, each made of one
> PCIe controller, two DesignWare XPCS instances and a shared 2-lane
> combo PHY. Add the phylink PCS driver for the XPCS instances, with 1G
> SGMII support.
> 
> The XPCS PMA/PLL bring-up is a property of the shared combo PHY: in the
> PCIe+SGMII modes the two XPCS instances share the PHY with the PCIe
> lane, so the XPCS cannot be a self-contained PCS platform device that
> owns its own reset/bring-up sequence. This driver therefore exposes a
> small init/bring-up API which the SerDes PHY driver sequences (it owns
> the shared PMA and enforces the required ordering, e.g. XPCS1 before
> XPCS0 in the dual-SGMII mode), while the phylink_pcs ops consumed by the
> MAC live here in the PCS driver. The MAC obtains its phylink PCS via
> [ ... ]
> Signed-off-by: Ionut Vicovan <Ionut.Vicovan at nxp.com>
> Co-developed-by: Bogdan Roman <bogdan-gabriel.roman at nxp.com>
> Signed-off-by: Bogdan Roman <bogdan-gabriel.roman at nxp.com>
> Co-developed-by: Jan Petrous (OSS) <jan.petrous at oss.nxp.com>
> Signed-off-by: Jan Petrous (OSS) <jan.petrous at oss.nxp.com>

Sashiko has reviewed this patch and found no issues. It looks great!

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260919-s32g_serdes-v3-0-9d68868c1e89@oss.nxp.com?part=5