[PATCH RFC v3 01/12] dt-bindings: phy: Add NXP S32G SerDes subsystem

sashiko-bot at kernel.org sashiko-bot at kernel.org
Sat Sep 19 23:54:55 PDT 2026


Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] dt-bindings: missing required enforcement for phy at 0 and phy at 1 nodes
--

commit 9e2cce806a48312a639c54029d5a8b84871dace7
Author: Jan Petrous (OSS) <jan.petrous at oss.nxp.com>

dt-bindings: phy: Add NXP S32G SerDes subsystem

This commit introduces the device tree binding for the NXP S32G2/S32G3 SerDes
subsystem. It defines the hardware constraints for the combo PHY shared
between PCIe and DesignWare XPCS instances, and specifies that both lanes
must always be described in the device tree.

> diff --git a/Documentation/devicetree/bindings/phy/nxp,s32g-serdes.yaml b/Documentation/devicetree/bindings/phy/nxp,s32g-serdes.yaml
> new file mode 100644
> index 0000000000000..6343d01bfde45
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/nxp,s32g-serdes.yaml

[ ... ]

> +patternProperties:
> +  '^phy@[01]$':
> +    description: One SerDes lane. The unit address is the physical lane index.
> +    type: object
> +    additionalProperties: false
> +
> +    properties:

[ ... ]

> +required:
> +  - compatible
> +  - reg
> +  - reg-names
> +  - clocks
> +  - clock-names
> +  - resets
> +  - reset-names
> +  - '#address-cells'
> +  - '#size-cells'

[Severity: Medium]
The commit message explicitly states "Both lanes must always be described, even
a lane the board does not wire out to a connector", but is the schema actually 
enforcing this?

The patternProperties block defines the schema for the lane child nodes, but it
only applies validation if those nodes are present. Because the phy at 0 and phy at 1
node names are missing from the top-level required list, it looks like a
device tree omitting them would silently pass dt_binding_check validation.

Since the driver will fail the probe with -EINVAL if the lanes are missing,
could these nodes be explicitly required in the schema to fully enforce the
stated hardware constraints?

> +
> +additionalProperties: false

[ ... ]

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260919-s32g_serdes-v3-0-9d68868c1e89@oss.nxp.com?part=1



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