[PATCH RFC v3 07/12] net: stmmac: dwmac-s32: Add SGMII support

[sashiko-bot at kernel.org]

> From: "Jan Petrous (OSS)" <jan.petrous at oss.nxp.com>
> 
> Wire the NXP S32G SerDes XPCS PCS into the dwmac-s32 glue layer so the
> MAC can run SGMII over a SerDes lane.
> 
> Changes:
> - s32_gmac_write_phy_intf_select: replace the hard-coded RGMII selector
>   with a switch on phy_interface so SGMII (0x01), RGMII, RMII and MII
>   all programme the SoC control register correctly.
> - Add s32_gmac_pcs_init: obtain the phylink_pcs handle from the SerDes
>   subsystem via s32g_serdes_pcs_create(), keyed by the standard
>   pcs-handle property on the GMAC node pointing at the SerDes XPCS lane
>   child. Propagates -EPROBE_DEFER if the SerDes driver has not probed
>   yet. There is no matching exit hook: the device link created by
>   s32g_serdes_pcs_create() covers the lifetime.
> [ ... ]
> Tested on an S32G3-VNP-RDB3 board: GMAC0 links at 1G over SGMII and
> passes traffic, both in SerDes mode 1 (alongside two active PCIe root
> complexes) and in mode 3.
> 
> Signed-off-by: Jan Petrous (OSS) <jan.petrous at oss.nxp.com>

Sashiko has reviewed this patch and found no issues. It looks great!

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Sashiko AI review · https://sashiko.dev/#/patchset/20260919-s32g_serdes-v3-0-9d68868c1e89@oss.nxp.com?part=7