[PATCH v16 10/11] arm64: dts: qcom: kaanapali: Add CCI controller nodes
hangxiang.ma at oss.qualcomm.com
hangxiang.ma at oss.qualcomm.com
Wed Sep 16 22:04:00 PDT 2026
On 9/15/26 9:16 PM, Loic Poulain <loic.poulain at oss.qualcomm.com> wrote:
> On Tue, Sep 15, 2026 at 12:10 PM Hangxiang Ma
> <hangxiang.ma at oss.qualcomm.com> wrote:
> >
> > Add the three Camera Control Interface (CCI) controllers present on the
> > Kaanapali SoC. Each controller provides two I2C hosts used for camera
> > sensor control, so define the controller nodes and their pinctrl states.
> >
> > The first bus has two CCI bus master pinouts:
> > cci_i2c_sda0 = gpio109
> > cci_i2c_scl0 = gpio110
> >
> > cci_i2c_sda1 = gpio111
> > cci_i2c_scl1 = gpio112
> >
> > The second bus has two CCI bus master pinouts:
> > cci_i2c_sda3 = gpio113
> > cci_i2c_scl3 = gpio114
> >
> > cci_i2c_sda4 = gpio107
> > cci_i2c_scl4 = gpio160
> >
> > The third bus has two CCI bus master pinouts:
> > cci_i2c_sda5 = gpio108
> > cci_i2c_scl5 = gpio149
> >
> > cci_i2c_sda6 = gpio115
> > cci_i2c_scl6 = gpio116
> >
> > Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy at linaro.org>
> > Signed-off-by: Hangxiang Ma <hangxiang.ma at oss.qualcomm.com>
>
> We used to configure an assigned-clock-rate for the CCI core clock to
> ensure it generates the desired CCI master bus frequency (for example,
> a 1 MHz bus requires a 37.5 MHz core clock). Is it safe to assume that
> the firmware, or the default platform configuration, already programs
> the core clock to the correct rate?
>
> Regards,
> Loic
>
>
>
>
> > ---
> > arch/arm64/boot/dts/qcom/kaanapali.dtsi | 303 ++++++++++++++++++++++++++++++++
> > 1 file changed, 303 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
> > index 84b93914ad53..02f8dab30b91 100644
> > --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
> > @@ -3514,6 +3514,117 @@ port at 5 {
> > };
> > };
> >
> > + cci0: cci at 941b000 {
> > + compatible = "qcom,kaanapali-cci", "qcom,msm8996-cci";
> > + reg = <0x0 0x0941b000 0x0 0x1000>;
> > +
> > + interrupts = <GIC_SPI 426 IRQ_TYPE_EDGE_RISING>;
> > +
> > + clocks = <&camcc CAM_CC_CAM_TOP_AHB_CLK>,
> > + <&camcc CAM_CC_CCI_0_CLK>;
> > + clock-names = "ahb",
> > + "cci";
> > +
> > + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
> > +
> > + pinctrl-0 = <&cci0_i2c0_default &cci0_i2c1_default>;
> > + pinctrl-1 = <&cci0_i2c0_sleep &cci0_i2c1_sleep>;
> > + pinctrl-names = "default", "sleep";
> > +
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + status = "disabled";
> > +
> > + cci0_i2c0: i2c-bus at 0 {
> > + reg = <0>;
> > + clock-frequency = <1000000>;
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + };
> > +
> > + cci0_i2c1: i2c-bus at 1 {
> > + reg = <1>;
> > + clock-frequency = <1000000>;
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + };
> > + };
> > +
> > + cci1: cci at 941c000 {
> > + compatible = "qcom,kaanapali-cci", "qcom,msm8996-cci";
> > + reg = <0x0 0x0941c000 0x0 0x1000>;
> > +
> > + interrupts = <GIC_SPI 427 IRQ_TYPE_EDGE_RISING>;
> > +
> > + clocks = <&camcc CAM_CC_CAM_TOP_AHB_CLK>,
> > + <&camcc CAM_CC_CCI_1_CLK>;
> > + clock-names = "ahb",
> > + "cci";
> > +
> > + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
> > +
> > + pinctrl-0 = <&cci1_i2c0_default &cci1_i2c1_default>;
> > + pinctrl-1 = <&cci1_i2c0_sleep &cci1_i2c1_sleep>;
> > + pinctrl-names = "default", "sleep";
> > +
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + status = "disabled";
> > +
> > + cci1_i2c0: i2c-bus at 0 {
> > + reg = <0>;
> > + clock-frequency = <1000000>;
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + };
> > +
> > + cci1_i2c1: i2c-bus at 1 {
> > + reg = <1>;
> > + clock-frequency = <1000000>;
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + };
> > + };
> > +
> > + cci2: cci at 941d000 {
> > + compatible = "qcom,kaanapali-cci", "qcom,msm8996-cci";
> > + reg = <0x0 0x0941d000 0x0 0x1000>;
> > +
> > + interrupts = <GIC_SPI 428 IRQ_TYPE_EDGE_RISING>;
> > +
> > + clocks = <&camcc CAM_CC_CAM_TOP_AHB_CLK>,
> > + <&camcc CAM_CC_CCI_2_CLK>;
> > + clock-names = "ahb",
> > + "cci";
> > +
> > + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
> > +
> > + pinctrl-0 = <&cci2_i2c0_default &cci2_i2c1_default>;
> > + pinctrl-1 = <&cci2_i2c0_sleep &cci2_i2c1_sleep>;
> > + pinctrl-names = "default", "sleep";
> > +
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + status = "disabled";
> > +
> > + cci2_i2c0: i2c-bus at 0 {
> > + reg = <0>;
> > + clock-frequency = <1000000>;
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + };
> > +
> > + cci2_i2c1: i2c-bus at 1 {
> > + reg = <1>;
> > + clock-frequency = <1000000>;
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + };
> > + };
> > +
> > csiphy0: phy at 9523000 {
> > compatible = "qcom,kaanapali-csi2-phy";
> > reg = <0x0 0x09523000 0x0 0x2000>;
> > @@ -4224,6 +4335,198 @@ tlmm: pinctrl at f100000 {
> > #interrupt-cells = <2>;
> > wakeup-parent = <&pdc>;
> >
> > + cci0_i2c0_default: cci0-i2c0-default-state {
> > + scl-pins {
> > + pins = "gpio110";
> > + function = "cci_i2c_scl";
> > + drive-strength = <2>;
> > + bias-pull-up;
> > + };
> > +
> > + sda-pins {
> > + pins = "gpio109";
> > + function = "cci_i2c_sda";
> > + drive-strength = <2>;
> > + bias-pull-up;
> > + };
> > + };
> > +
> > + cci0_i2c0_sleep: cci0-i2c0-sleep-state {
> > + scl-pins {
> > + pins = "gpio110";
> > + function = "cci_i2c_scl";
> > + drive-strength = <2>;
> > + bias-pull-down;
> > + };
> > +
> > + sda-pins {
> > + pins = "gpio109";
> > + function = "cci_i2c_sda";
> > + drive-strength = <2>;
> > + bias-pull-down;
> > + };
> > + };
> > +
> > + cci0_i2c1_default: cci0-i2c1-default-state {
> > + scl-pins {
> > + pins = "gpio112";
> > + function = "cci_i2c_scl";
> > + drive-strength = <2>;
> > + bias-pull-up;
> > + };
> > +
> > + sda-pins {
> > + pins = "gpio111";
> > + function = "cci_i2c_sda";
> > + drive-strength = <2>;
> > + bias-pull-up;
> > + };
> > + };
> > +
> > + cci0_i2c1_sleep: cci0-i2c1-sleep-state {
> > + scl-pins {
> > + pins = "gpio112";
> > + function = "cci_i2c_scl";
> > + drive-strength = <2>;
> > + bias-pull-down;
> > + };
> > +
> > + sda-pins {
> > + pins = "gpio111";
> > + function = "cci_i2c_sda";
> > + drive-strength = <2>;
> > + bias-pull-down;
> > + };
> > + };
> > +
> > + cci1_i2c0_default: cci1-i2c0-default-state {
> > + scl-pins {
> > + pins = "gpio114";
> > + function = "cci_i2c_scl";
> > + drive-strength = <2>;
> > + bias-pull-up;
> > + };
> > +
> > + sda-pins {
> > + pins = "gpio113";
> > + function = "cci_i2c_sda";
> > + drive-strength = <2>;
> > + bias-pull-up;
> > + };
> > + };
> > +
> > + cci1_i2c0_sleep: cci1-i2c0-sleep-state {
> > + scl-pins {
> > + pins = "gpio114";
> > + function = "cci_i2c_scl";
> > + drive-strength = <2>;
> > + bias-pull-down;
> > + };
> > +
> > + sda-pins {
> > + pins = "gpio113";
> > + function = "cci_i2c_sda";
> > + drive-strength = <2>;
> > + bias-pull-down;
> > + };
> > + };
> > +
> > + cci1_i2c1_default: cci1-i2c1-default-state {
> > + scl-pins {
> > + pins = "gpio160";
> > + function = "cci_i2c_scl";
> > + drive-strength = <2>;
> > + bias-pull-up;
> > + };
> > +
> > + sda-pins {
> > + pins = "gpio107";
> > + function = "cci_i2c_sda";
> > + drive-strength = <2>;
> > + bias-pull-up;
> > + };
> > + };
> > +
> > + cci1_i2c1_sleep: cci1-i2c1-sleep-state {
> > + scl-pins {
> > + pins = "gpio160";
> > + function = "cci_i2c_scl";
> > + drive-strength = <2>;
> > + bias-pull-down;
> > + };
> > +
> > + sda-pins {
> > + pins = "gpio107";
> > + function = "cci_i2c_sda";
> > + drive-strength = <2>;
> > + bias-pull-down;
> > + };
> > + };
> > +
> > + cci2_i2c0_default: cci2-i2c0-default-state {
> > + scl-pins {
> > + pins = "gpio149";
> > + function = "cci_i2c_scl";
> > + drive-strength = <2>;
> > + bias-pull-up;
> > + };
> > +
> > + sda-pins {
> > + pins = "gpio108";
> > + function = "cci_i2c_sda";
> > + drive-strength = <2>;
> > + bias-pull-up;
> > + };
> > + };
> > +
> > + cci2_i2c0_sleep: cci2-i2c0-sleep-state {
> > + scl-pins {
> > + pins = "gpio149";
> > + function = "cci_i2c_scl";
> > + drive-strength = <2>;
> > + bias-pull-down;
> > + };
> > +
> > + sda-pins {
> > + pins = "gpio108";
> > + function = "cci_i2c_sda";
> > + drive-strength = <2>;
> > + bias-pull-down;
> > + };
> > + };
> > +
> > + cci2_i2c1_default: cci2-i2c1-default-state {
> > + scl-pins {
> > + pins = "gpio116";
> > + function = "cci_i2c_scl";
> > + drive-strength = <2>;
> > + bias-pull-up;
> > + };
> > +
> > + sda-pins {
> > + pins = "gpio115";
> > + function = "cci_i2c_sda";
> > + drive-strength = <2>;
> > + bias-pull-up;
> > + };
> > + };
> > +
> > + cci2_i2c1_sleep: cci2-i2c1-sleep-state {
> > + scl-pins {
> > + pins = "gpio116";
> > + function = "cci_i2c_scl";
> > + drive-strength = <2>;
> > + bias-pull-down;
> > + };
> > +
> > + sda-pins {
> > + pins = "gpio115";
> > + function = "cci_i2c_sda";
> > + drive-strength = <2>;
> > + bias-pull-down;
> > + };
> > + };
> > +
> > hub_i2c0_data_clk: hub-i2c0-data-clk-state {
> > /* SDA, SCL */
> > pins = "gpio66", "gpio67";
> >
> > --
> > 2.34.1
> >
>
Hi, this is safe on KNP. The CCI source clock is derived from the PLL0 even clock through a fixed divider, which results in a fixed 37.5 MHz CCI core clock. As a result, no assigned-clock-rate property is required on this platform.
Other platforms may have different clock topologies and should be evaluated independently. Thanks for your attention.
Best regards,
Hangxiang
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