[PATCH v18 1/2] dt-bindings: phy: qcom: Add CSI2 C-PHY/DPHY schema
sashiko-bot at kernel.org
sashiko-bot at kernel.org
Wed Sep 16 17:05:37 PDT 2026
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] dt-bindings: phy: qcom: Incomplete constraints for DPHY split-mode
--
commit f4a95bb9fcce6ee77a3c3f8e0b0bc0bc538a0aa7
Author: Bryan O'Donoghue <bryan.odonoghue at linaro.org>
dt-bindings: phy: qcom: Add CSI2 C-PHY/DPHY schema
Add a base schema for the MIPI CSI2 PHYs on Qualcomm SoCs. The schema
supports both C-PHY and D-PHY modes, as well as a split-mode allowing two
sensors to be connected to one PHY.
> diff --git a/Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml
> new file mode 100644
> index 0000000000000..dc64af97da6c6
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml
[ ... ]
> + allOf:
> + - if:
> + required:
> + - endpoint at 1
> + then:
> + properties:
> + endpoint at 0:
> + properties:
> + data-lanes:
> + maxItems: 2
> + items:
> + maximum: 2
> + endpoint at 1:
> + properties:
> + data-lanes:
> + items:
> + - const: 3
[Severity: Low]
Does this schema lack sufficient constraints for the split-mode endpoints?
The split-mode definition in properties.ports.properties.port at 0.allOf appears
to be missing bus-type restrictions, clock-lanes constraints, and an explicit
maxItems restriction for endpoint at 1. Without these, a misconfigured device
tree utilizing split-mode with an invalid bus-type, incorrect clock-lanes, or
extra data-lanes on endpoint at 1 will pass dt-schema validation silently.
Could explicit constraints be added here to enforce the D-PHY bus-type,
restrict the clock-lanes positions, and strictly limit maxItems?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260917-x1e-csi2-phy-v18-0-6515b5255fa9@linaro.org?part=1
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