[PATCH v2 3/3] phy: qcom: qmp-combo: Add USB3+DP PHY support for Nord

[sashiko-bot at kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] phy: qcom: mismatch between commit message and nord_usb3_tx_tbl
--

commit 1b7c23f467a9a0ffe85f80b15fdee3ce3ad5c895
Author: Bartosz Golaszewski <bartosz.golaszewski at oss.qualcomm.com>

phy: qcom: qmp-combo: Add USB3+DP PHY support for Nord

Nord SoC provides two USB3+DP combo PHYs. Their initialisation sequences
are identical to sm8550, but the sub-blocks are not laid out the same way.
A dedicated USB3_PCS_AON region at offset 0x1e00 is added, modifying how
the I/O clamp is driven.

> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> index a4f130fc33e39..c4e88b0384cb5 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> @@ -2356,6 +2356,20 @@ static const struct qmp_phy_init_tbl hawi_usb3_pcs_usb_tbl[] = {
>  	QMP_PHY_INIT_CFG(QPHY_V10_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),
>  };
>  
> +static const struct qmp_phy_init_tbl nord_usb3_tx_tbl[] = {
> +	QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_TX, 0x00),
> +	QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_RX, 0x00),
> +	QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
> +	QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
> +	QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0xf5),
> +	QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_3, 0x3f),
> +	QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_4, 0x3f),
> +	QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_5, 0x5f),
> +	QMP_PHY_INIT_CFG(QSERDES_V6_TX_RCV_DETECT_LVL_2, 0x14),

[Severity: Medium]
The commit message claims that the initialization sequences are identical to
sm8550. However, this configures QSERDES_V6_TX_RCV_DETECT_LVL_2 to 0x14,
whereas sm8550 uses 0x12.

Is this an intentional hardware difference for Nord that should be mentioned
in the commit message, or is it an accidental typo?

> +	QMP_PHY_INIT_CFG_LANE(QSERDES_V6_TX_PI_QEC_CTRL, 0x21, 1),
> +	QMP_PHY_INIT_CFG_LANE(QSERDES_V6_TX_PI_QEC_CTRL, 0x05, 2),
> +};

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260916-nord-usb-phy-v2-0-2c8461bb30e6@oss.qualcomm.com?part=3