[PATCH 3/4] phy: qcom-qmp-pcie-multiphy: Split phy_ops into init/exit/reset/power_on

[sashiko-bot at kernel.org]

> Per HPG, the controller now calls phy_init() from
> qcom_pcie_host_init() and phy_reset() from inside its own core reset
> assert/deassert. Making that actually happen here needs phy_ops::init
> and phy_ops::reset implemented, and phy_ops::power_on adjusted to
> match. Split the combined phy_ops::power_on/power_off into
> phy_ops::init/exit/reset/power_on to do that.
> 
> phy_ops::init enables power domains, regulators, and all PHY clocks
> (pipe clock first). phy_ops::reset does the no-CSR reset assert/
> delay/deassert/delay. phy_ops::power_on is left with just the PCS
> status poll. phy_ops::exit mirrors phy_ops::init in reverse;
> phy_ops::power_off is dropped since nothing remains for it to do.
> 
> Signed-off-by: Qiang Yu <qiang.yu at oss.qualcomm.com>

Sashiko has reviewed this patch and found no issues. It looks great!

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Sashiko AI review · https://sashiko.dev/#/patchset/20260915-align_pcie_init_sequence_0916-v1-0-0b2195836f30@oss.qualcomm.com?part=3