[PATCH v4 7/9] phy: qualcomm: qmp-combo: Update qmp_v8_configure_dp_clocks() for Glymur

[Manivannan Sadhasivam]

On Tue, Sep 08, 2026 at 07:31:00PM +0530, Nabige Aala wrote:
> From: Ritesh Kumar <ritesh.kumar at oss.qualcomm.com>
> 
> Remove VCO_DIV programming from qmp_v8_configure_dp_clocks() as it is
> not required for the v8 PHY.
> 
> Add per-link-rate auxless setup/silence cycle and LFPS period values
> instead of using fixed constants:
>   RBR (1.62 Gbps): setup=0x03, silence=0x06, lfps_period=0x00
>   HBR (2.70 Gbps): setup=0x04, silence=0x08, lfps_period=0x11
>   HBR2 (5.40 Gbps): setup=0x09, silence=0x11, lfps_period=0x33
>   HBR3 (8.10 Gbps): setup=0x0f, silence=0x1a, lfps_period=0x55
> 

Why is this change needed?

> Add per-lane drive level lookup from the ln_drv_lvl tables based on
> the maximum voltage swing and pre-emphasis levels across all active
> lanes, replacing the hardcoded 0x1f value.
> 

Same here.

> Remove the duplicate LFPS_PERIOD write that was present after the
> AUXLESS_CFG1 programming.
> 

Again, you've clubbed multiple changes in a single patch :/

> Fixes: d10736db98d25 ("phy: qualcomm: qmp-combo: Add DP offsets and settings for Glymur platforms")

What is the issue the patch is fixing?

- Mani

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