[PATCH v3 3/5] PCI: qcom: Add CGC disable workaround for Nord PCIe

[Manivannan Sadhasivam]

On Thu, Sep 10, 2026 at 09:29:10AM +0200, Konrad Dybcio wrote:
> On 9/10/26 9:20 AM, Manivannan Sadhasivam wrote:
> > On Wed, Sep 09, 2026 at 05:18:18PM +0530, Krishna Chaitanya Chundru wrote:
> >> Nord requires a workaround to address a timing convergence issue in the
> >> PCIe power domain. To avoid the issue, set the CORE_CLK_CGC_DIS and
> >> AUX_PWR_DET bits in PARF_SYS_CTRL after controller initialization.
> 
> [...]
> 
> >> +static const struct qcom_pcie_cfg cfg_nord = {
> > 
> > Can you use DWC IP version instead of SoC name?
> 
> I'd say it's fine given other implementations of the same DWC IP may not
> have this clock gating quirk
> 

Hmm, fair point.

- Mani

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