[PATCH v3 1/5] dt-bindings: phy: qcom: add Nord QMP PCIe PHY binding

[Manivannan Sadhasivam]

On Wed, Sep 09, 2026 at 05:18:16PM +0530, Krishna Chaitanya Chundru wrote:
> Document the PCIe PHY found on the Qualcomm Nord platform.
> 
> Nord has a Gen5-capable QMP PCIe PHY that can operate in multiple

Use data rate instead of 'Gen'.

> lane configurations using four PHY segments (A/B/C/D). The active
> topology is selected by firmware through a TCSR configuration
> register and may be configured as x16, x8+x8, x8+x4+x4, or
> x8+x4+x2+x2.
> 
> The binding describes the register regions, clocks, resets, power
> domains, regulators, PHY provider interface, clock provider interface,
> and the qcom,link-mode property used by the driver to discover the
> active lane configuration programmed by firmware.
> 
> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru at oss.qualcomm.com>
> ---
>  .../phy/qcom,nord-qmp-gen5x16-pcie-phy.yaml        | 272 +++++++++++++++++++++
>  1 file changed, 272 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/phy/qcom,nord-qmp-gen5x16-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,nord-qmp-gen5x16-pcie-phy.yaml
> new file mode 100644
> index 000000000000..624ad7e7d13e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/qcom,nord-qmp-gen5x16-pcie-phy.yaml
> @@ -0,0 +1,272 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/qcom,nord-qmp-gen5x16-pcie-phy.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm Nord QMP Quadfurcated PCIe multiple link-mode PHY
> +
> +maintainers:
> +  - Krishna Chaitanya Chundru <krishna.chundru at oss.qualcomm.com>
> +
> +description: |
> +  The Qualcomm Nord PCIe PHY is a Gen5-capable QMP PCIe PHY composed
> +  of four PHY ports (A/B/C/D). The ports can be combined to support
> +  multiple lane topologies, including x16, x8+x8, x8+x4+x4 and
> +  x8+x4+x2+x2 configurations.
> +
> +  The selected topology is determined by the PCIe link configuration mode
> +  programmed in TCSR registers. Depending on the selected mode, PHY ports
> +  may operate independently or be grouped together to form wider PCIe links.
> +
> +  Each port provides dedicated register space, clocks, resets and power
> +  resources required for PHY operation.
> +
> +properties:
> +  compatible:
> +    enum:
> +      - qcom,nord-qmp-gen5x16-pcie-phy
> +
> +  reg:
> +    maxItems: 4
> +
> +  reg-names:
> +    items:
> +      - const: port_a
> +      - const: port_b
> +      - const: port_c
> +      - const: port_d
> +
> +  clocks:
> +    maxItems: 17
> +
> +  clock-names:
> +    items:
> +      - const: aux_a
> +      - const: cfg_ahb_a
> +      - const: ref
> +      - const: rchng_a
> +      - const: pipe_a
> +      - const: aux_b
> +      - const: cfg_ahb_b
> +      - const: rchng_b
> +      - const: pipe_b
> +      - const: aux_c
> +      - const: cfg_ahb_c
> +      - const: rchng_c
> +      - const: pipe_c
> +      - const: aux_d
> +      - const: cfg_ahb_d
> +      - const: rchng_d
> +      - const: pipe_d
> +
> +  power-domains:
> +    maxItems: 4
> +
> +  power-domain-names:
> +    items:
> +      - const: port_a
> +      - const: port_b
> +      - const: port_c
> +      - const: port_d
> +
> +  resets:
> +    maxItems: 8
> +
> +  reset-names:
> +    items:
> +      - const: port_a
> +      - const: port_a_nocsr
> +      - const: port_b
> +      - const: port_b_nocsr
> +      - const: port_c
> +      - const: port_c_nocsr
> +      - const: port_d
> +      - const: port_d_nocsr
> +
> +  vdda-phy-a-supply: true
> +
> +  vdda-phy-b-supply: true
> +
> +  vdda-phy-c-supply: true
> +
> +  vdda-phy-d-supply: true
> +
> +  vdda-pll-a-supply: true
> +
> +  vdda-pll-b-supply: true
> +
> +  vdda-pll-c-supply: true
> +
> +  vdda-pll-d-supply: true
> +
> +  qcom,link-mode:
> +    description: |
> +      Reference to the TCSR syscon and the offset of the
> +      TCSR_PCIE_LINK_CONFIG_MODE register.
> +        0 (QMP_PCIE_NORD_MODE_X16)        — all ports ganged as x16
> +        1 (QMP_PCIE_NORD_MODE_X8_X8)      — x8 (port A) + x8 (port B+C+D)
> +        2 (QMP_PCIE_NORD_MODE_X8_X4_X4)   — x8 (A) + x4 (B) + x4 (C+D)
> +        3 (QMP_PCIE_NORD_MODE_X8_X4_X2_X2)— x8 (A) + x4 (B) + x2 (C) + x2 (D)
> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +    items:
> +      - items:
> +          - description: Phandle of the TCSR syscon
> +          - description: Offset of TCSR_PCIE_LINK_CONFIG_MODE register
> +
> +  "#clock-cells":
> +    const: 1
> +    description:
> +      Selects the pipe clock output by port index (0=A, 1=B, 2=C, 3=D).
> +      GCC pipe-clock mux parents reference this provider.
> +
> +  clock-output-names:
> +    items:
> +      - description: Name of the PHY A pipe clock output.
> +      - description: Name of the PHY B pipe clock output.
> +      - description: Name of the PHY C pipe clock output.
> +      - description: Name of the PHY D pipe clock output.
> +
> +  "#phy-cells":
> +    const: 1
> +    description: |
> +      Selects the PHY instance by index:
> +        0 — port A (up to Gen5 x8; anchor in x16 mode)
> +        1 — port B (up to Gen5 x4)
> +        2 — port C (up to Gen5 x2)
> +        3 — port D (up to Gen5 x2)
> +
> +required:
> +  - compatible
> +  - reg
> +  - reg-names
> +  - clocks
> +  - clock-names
> +  - power-domains
> +  - power-domain-names
> +  - resets
> +  - reset-names
> +  - vdda-phy-a-supply
> +  - vdda-phy-b-supply
> +  - vdda-phy-c-supply
> +  - vdda-phy-d-supply
> +  - vdda-pll-a-supply
> +  - vdda-pll-b-supply
> +  - vdda-pll-c-supply
> +  - vdda-pll-d-supply
> +  - qcom,link-mode
> +  - "#clock-cells"
> +  - clock-output-names
> +  - "#phy-cells"
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/clock/qcom,nord-gcc.h>
> +    #include <dt-bindings/clock/qcom,nord-tcsrcc.h>
> +
> +    soc {
> +        #address-cells = <2>;
> +        #size-cells = <2>;
> +

Drop 'soc' and address/size cells and use 32bit addresses for 'reg'.

- Mani

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