[PATCH v3 3/5] PCI: qcom: Add CGC disable workaround for Nord PCIe
Shawn Guo
shengchao.guo at oss.qualcomm.com
Wed Sep 9 23:47:24 PDT 2026
On Wed, Sep 09, 2026 at 05:18:18PM +0530, Krishna Chaitanya Chundru wrote:
> Nord requires a workaround to address a timing convergence issue in the
> PCIe power domain. To avoid the issue, set the CORE_CLK_CGC_DIS and
> AUX_PWR_DET bits in PARF_SYS_CTRL after controller initialization.
>
> The SLV_ACLK_CGC_DIS bit is already configured by hardware reset. This
> change adds the remaining required settings as documented in
> QCTDD11972446.
>
> Reviewed-by: Konrad Dybcio <konrad.dybcio at oss.qualcomm.com>
> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru at oss.qualcomm.com>
Reviewed-by: Shawn Guo <shengchao.guo at oss.qualcomm.com>
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