[PATCH v7 4/4] phy: ti-pipe3: Fix clock leak in init error path

[sashiko-bot at kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The patch includes an undocumented fix for a clock leak in the SATA normal exit path.
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commit ca88937817d44eb924ea2b35541539f033e6efa9
Author: Hongling Zeng <zenghongling at kylinos.cn>

phy: ti-pipe3: Fix clock leak in init error path

When regmap_update_bits() fails in ti_pipe3_init() for PCIe mode,
the function returns the error without calling ti_pipe3_disable_clocks().
This leaves the clocks permanently enabled since the PHY framework won't
invoke the .exit callback on init failure.

Link: https://lore.kernel.org/all/20260518023657.41852C2BCB0@smtp.kernel.org/

> diff --git a/drivers/phy/ti/phy-ti-pipe3.c b/drivers/phy/ti/phy-ti-pipe3.c
> index a67f5da43c83b..fea64db93da54 100644
> --- a/drivers/phy/ti/phy-ti-pipe3.c
> +++ b/drivers/phy/ti/phy-ti-pipe3.c
[ ... ]
> @@ -555,8 +557,10 @@ static int ti_pipe3_exit(struct phy *x)
>  	/* If dpll_reset_syscon is not present we wont power down SATA DPLL
>  	 * due to Errata i783
>  	 */
> -	if (phy->mode == PIPE3_MODE_SATA && !phy->dpll_reset_syscon)
> +	if (phy->mode == PIPE3_MODE_SATA && !phy->dpll_reset_syscon) {
> +		ti_pipe3_disable_clocks(phy);
>  		return 0;
> +	}
>  
>  	/* PCIe doesn't have internal DPLL */
>  	if (phy->mode != PIPE3_MODE_PCIE) {

[Severity: Medium]
Does the commit message need to document this fix in the SATA exit path?

The commit message only mentions fixing the clock leak in the ti_pipe3_init()
error path for PCIe mode. 

This addition of ti_pipe3_disable_clocks() in ti_pipe3_exit() for the SATA
mode seems like a meaningful functional change that isn't documented in the
commit log, which could cause confusion during review and hinder stable
backports.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260909113433.1287454-1-zenghongling@kylinos.cn?part=4