[PATCH v4 1/9] phy: qualcomm: qmp-combo: Add DP COM v8 header and fix register layout

[sashiko-bot at kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] Incomplete migration to DP COM v8 macros in `qmp_v8_n3_usb43dpphy_regs_layout`.
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commit 7145547c9c8156e9bd6b404c8a392eeca721fb95
Author: Ritesh Kumar <ritesh.kumar at oss.qualcomm.com>

phy: qualcomm: qmp-combo: Add DP COM v8 header and fix register layout

Add the new DP-specific QSERDES COM v8 header file and update the
register layout to use DP-specific status register offsets for
C_READY_STATUS and CMN_STATUS registers.

> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> index c39ced168d035..4d31637f1dce6 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c

[ ... ]

> @@ -318,8 +319,8 @@ static const unsigned int qmp_v8_n3_usb43dpphy_regs_layout[QPHY_LAYOUT_SIZE] = {
>  	[QPHY_DP_AON_TOGGLE_ENABLE]		= QPHY_V8_PCS_AON_DP_AON_TOGGLE_ENABLE,
>  
>  	[QPHY_COM_RESETSM_CNTRL]		= QSERDES_V8_COM_RESETSM_CNTRL,

[Severity: Low]
Should this also be updated to the new DP macro DP_QSERDES_V8_COM_RESETSM_CNTRL?

It looks like we're mixing USB and DP COM macros for DP Serdes configuration
registers here in qmp_v8_n3_usb43dpphy_regs_layout.

> -	[QPHY_COM_C_READY_STATUS]		= QSERDES_V8_COM_C_READY_STATUS,
> -	[QPHY_COM_CMN_STATUS]			= QSERDES_V8_COM_CMN_STATUS,
> +	[QPHY_COM_C_READY_STATUS]		= DP_QSERDES_V8_COM_C_READY_STATUS,
> +	[QPHY_COM_CMN_STATUS]			= DP_QSERDES_V8_COM_CMN_STATUS,
>  	[QPHY_COM_BIAS_EN_CLKBUFLR_EN]	= QSERDES_V8_COM_BIAS_EN_CLKBUFLR_EN,

[Severity: Low]
Does QPHY_COM_BIAS_EN_CLKBUFLR_EN also need updating to
DP_QSERDES_V8_COM_BIAS_EN_CLKBUFLR_EN to be consistent with the changes above?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260908-glymur-phy-v3-v4-0-ff22e5150538@oss.qualcomm.com?part=1