[PATCH] phy: phy-snps-eusb2: fix FSEL_48_MHZ_VAL definition

[Xu Yang]

From: Xu Yang <xu.yang_2 at nxp.com>

According to Synopsys eUSB2 PHY Databook, FSEL_48_MHZ_VAL should be 0x6
for supported 48 MHz reference clock.

Fixes: c4098f3e6134 ("phy: phy-snps-eusb2: add support for exynos2200")
Cc: stable at vger.kernel.org
Signed-off-by: Xu Yang <xu.yang_2 at nxp.com>
---
 drivers/phy/phy-snps-eusb2.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/phy/phy-snps-eusb2.c b/drivers/phy/phy-snps-eusb2.c
index af4fa17ac6cb..3cb18d6ebc1d 100644
--- a/drivers/phy/phy-snps-eusb2.c
+++ b/drivers/phy/phy-snps-eusb2.c
@@ -21,7 +21,7 @@
 #define FSEL_20_MHZ_VAL			(0x1)
 #define FSEL_24_MHZ_VAL			(0x2)
 #define FSEL_26_MHZ_VAL			(0x3)
-#define FSEL_48_MHZ_VAL			(0x2)
+#define FSEL_48_MHZ_VAL			(0x6)
 
 #define EXYNOS_USB_PHY_CFG_PLLCFG0	(0x8)
 #define PHY_CFG_PLL_FB_DIV_19_8_MASK	GENMASK(19, 8)
-- 
2.34.1