[PATCH v3 2/4] phy: qualcomm: qmp-combo: Update DP PHY common init tables

[Manivannan Sadhasivam]

On Fri, Aug 28, 2026 at 03:13:14PM +0530, Nabige Aala wrote:
> From: Ritesh Kumar <ritesh.kumar at oss.qualcomm.com>
> 
> Update common DP PHY serdes and TX initialization tables with
> corrected PLL control values (MODE0 instead of MODE1), updated
> SSC step size, reset control, and various TX lane configuration
> parameters including emphasis levels and driver enable settings.
> 
> Signed-off-by: Ritesh Kumar <ritesh.kumar at oss.qualcomm.com>
> Signed-off-by: Mahadevan P <mahadevan.p at oss.qualcomm.com>
> Signed-off-by: Nabige Aala <nabige.aala at oss.qualcomm.com>

Missing Fixes tag as the update sounds like a fix.

Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam at oss.qualcomm.com>

- Mani

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