[PATCH v3 02/12] dt-bindings: phy: qcom,ipq5332-uniphy-pcie-usb3: Document the IPQ5018 USB3 PHY

Manivannan Sadhasivam mani at kernel.org
Mon Sep 7 04:08:55 PDT 2026


On Tue, Aug 25, 2026 at 04:37:19PM +0400, George Moussalem via B4 Relay wrote:
> From: George Moussalem <george.moussalem at outlook.com>
> 
> Describe the USB3 PHY found in the IPQ5018 SoC so add the compatible
> string for it as well as the required resources (clocks and resets).
> 
> The PCIe and USB physical pads are muxed and selection is done via a
> control register in TCSR. By default, PCIe mode is selected, hence make
> the property for USB mux selection required.
> 
> In addition, the PHY requires a 5V supply for USB3 mode operation.
> 
> Signed-off-by: George Moussalem <george.moussalem at outlook.com>
> ---
>  .../phy/qcom,ipq5332-uniphy-pcie-usb3-phy.yaml     | 24 ++++++++++++++++++++++
>  1 file changed, 24 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-pcie-usb3-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-pcie-usb3-phy.yaml
> index 0d9d0fb405b6..1cd5392a1a0f 100644
> --- a/Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-pcie-usb3-phy.yaml
> +++ b/Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-pcie-usb3-phy.yaml
> @@ -18,6 +18,7 @@ properties:
>    compatible:
>      enum:
>        - qcom,ipq5018-uniphy-pcie-phy
> +      - qcom,ipq5018-uniphy-usb3-phy
>        - qcom,ipq5332-uniphy-pcie-phy
>  
>    reg:
> @@ -93,6 +94,29 @@ allOf:
>        required:
>          - num-lanes
>  
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            enum:
> +              - qcom,ipq5018-uniphy-usb3-phy
> +    then:
> +      properties:
> +        clocks:
> +          items:
> +            - description: usb3 pipe clock
> +            - description: usb3 cfg ahb clock
> +        resets:
> +          items:
> +            - description: usb3 phy reset
> +        "#clock-cells":
> +          const: 0
> +        "#phy-cells":
> +          const: 0

clock-cells and phy-cells are already part of the top level 'required'
constraint.

- Mani

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