[PATCH 2/2] phy: qcom: edp: update v8 power-on programming sequence

[Christian Cortner]

Hi Konrad, Bjorn,

On the Asus Zenbook A16 (glymur, eDP at 5.4 Gbps), this series with
Konrad's TXn_LDO_CONFIG value (0x91) fell back to 2 lanes on 14 of
120 link enables, with bit errors on lanes 1 and 3.

The firmware ends power-on with five registers set differently:

  DP_PHY_CFG_1             0x2f -> 0x0f  (the bit 5 Konrad flagged)
  DP_PHY_TX2_TX3_LANE_CTL  0x05 -> 0x00
  TXn_RESET_TSYNC_EN       0x0a -> 0x03
  DP_PHY_TSYNC_OVRD        0x3e -> 0x10
  DP_PHY_CFG after DCC     0x09 -> 0x19

Writing the firmware values at the end of power-on, all 120 enables
over two boots trained 4 lanes cleanly, and 10 of 10 resumes. Which
register matters is not known. Happy to test a revision.

Christian