[PATCH v2 4/7] media: qcom: camss: Add SM8450 CAMSS support

[Frank Li]

On Tue, Oct 27, 2026 at 12:49:54AM +0200, Vladimir Zapolskiy wrote:
> Add support of the camera subsystem (CAMSS) found on Qualcomm SM8450 SoC.
>
> The CAMSS IP on SM8450 contains:
> * three CSID and two CSID lite, which are supported by CSID 680,
> * three VFE and two VFE lite blocks, which are supported by VFE 680,
> * three CSI test pattern generators, which are supported by TPG Gen1.
>
> Qualcomm SM8450 CSIPHYs are supported by the CSI2 PHY driver only.
>
> Signed-off-by: Vladimir Zapolskiy <vz at kernel.org>
> ---
>  drivers/media/platform/qcom/camss/camss-vfe.c |   2 +
>  drivers/media/platform/qcom/camss/camss.c     | 236 ++++++++++++++++++
>  drivers/media/platform/qcom/camss/camss.h     |   1 +
>  3 files changed, 239 insertions(+)
>
> diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c b/drivers/media/platform/qcom/camss/camss-vfe.c
> index 2680a9914765..8ebd67bd9b2e 100644
> --- a/drivers/media/platform/qcom/camss/camss-vfe.c
> +++ b/drivers/media/platform/qcom/camss/camss-vfe.c
> @@ -350,6 +350,7 @@ static u32 vfe_src_pad_code(struct vfe_line *line, u32 sink_code,
>  	case CAMSS_8280XP:
>  	case CAMSS_8300:
>  	case CAMSS_845:
> +	case CAMSS_8450:
>  	case CAMSS_8550:
>  	case CAMSS_8650:
>  	case CAMSS_8775P:
> @@ -2010,6 +2011,7 @@ static int vfe_bpl_align_rdi(struct vfe_device *vfe)
>  	case CAMSS_8280XP:
>  	case CAMSS_8300:
>  	case CAMSS_845:
> +	case CAMSS_8450:
>  	case CAMSS_8550:
>  	case CAMSS_8650:
>  	case CAMSS_8775P:
> diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
> index b0d60e70e4bb..1db66976e51b 100644
> --- a/drivers/media/platform/qcom/camss/camss.c
> +++ b/drivers/media/platform/qcom/camss/camss.c
> @@ -2967,6 +2967,226 @@ static const struct resources_icc icc_res_sc8280xp[] = {
>  	},
>  };
>
> +static const struct camss_subdev_resources csid_res_sm8450[] = {
> +	/* CSID0 */
> +	{
> +		.regulators = {},
> +		.clock = { "cpas_ahb", "csid", "csiphy_rx" },
> +		.clock_rate = { { 0 },
> +				{ 480000000 },
> +				{ 400000000 }, },
> +		.reg = { "csid0" },
> +		.interrupt = { "csid0" },
> +		.csid = {
> +			.hw_ops = &csid_ops_680,
> +			.parent_dev_ops = &vfe_parent_dev_ops,
> +			.formats = &csid_formats_gen2,
> +		},
> +	},
> +	/* CSID1 */
> +	{
> +		.regulators = {},
> +		.clock = { "cpas_ahb", "csid", "csiphy_rx" },
> +		.clock_rate = { { 0 },
> +				{ 480000000 },
> +				{ 400000000 }, },
> +		.reg = { "csid1" },
> +		.interrupt = { "csid1" },
> +		.csid = {
> +			.hw_ops = &csid_ops_680,
> +			.parent_dev_ops = &vfe_parent_dev_ops,
> +			.formats = &csid_formats_gen2,
> +		},
> +	},
> +	/* CSID2 */
> +	{
> +		.regulators = {},
> +		.clock = { "cpas_ahb", "csid", "csiphy_rx" },
> +		.clock_rate = { { 0 },
> +				{ 480000000 },
> +				{ 400000000 }, },
> +		.reg = { "csid2" },
> +		.interrupt = { "csid2" },
> +		.csid = {
> +			.hw_ops = &csid_ops_680,
> +			.parent_dev_ops = &vfe_parent_dev_ops,
> +			.formats = &csid_formats_gen2,
> +		},
> +	},
> +	/* CSID_LITE0 */
> +	{
> +		.regulators = {},
> +		.clock = { "cpas_ahb", "vfe_lite_csid", "vfe_lite_cphy_rx",
> +			   "csiphy_rx" },
> +		.clock_rate = { { 0 },
> +				{ 480000000 },
> +				{ 400000000 },
> +				{ 400000000 }, },
> +		.reg = { "csid_lite0" },
> +		.interrupt = { "csid_lite0" },
> +		.csid = {
> +			.is_lite = true,
> +			.hw_ops = &csid_ops_680,
> +			.parent_dev_ops = &vfe_parent_dev_ops,
> +			.formats = &csid_formats_gen2,
> +		},
> +	},
> +	/* CSID_LITE1 */
> +	{
> +		.regulators = {},
> +		.clock = { "cpas_ahb", "vfe_lite_csid", "vfe_lite_cphy_rx",
> +			   "csiphy_rx" },
> +		.clock_rate = { { 0 },
> +				{ 480000000 },
> +				{ 400000000 },
> +				{ 400000000 }, },
> +		.reg = { "csid_lite1" },
> +		.interrupt = { "csid_lite1" },
> +		.csid = {
> +			.is_lite = true,
> +			.hw_ops = &csid_ops_680,
> +			.parent_dev_ops = &vfe_parent_dev_ops,
> +			.formats = &csid_formats_gen2,
> +		},
> +	},
> +};
> +
> +static const struct camss_subdev_resources vfe_res_sm8450[] = {
> +	/* IFE0 */
> +	{
> +		.regulators = {},
> +		.clock = { "gcc_hf_axi", "camnoc_axi", "cpas_ahb",
> +			   "core_ahb", "cpas_fast_ahb", "cpas_vfe0",
> +			   "vfe0_fast_ahb", "vfe0" },
> +		.clock_rate = { { 0 },
> +				{ 300000000, 400000000 },
> +				{ 0 },
> +				{ 0 },
> +				{ 0 },
> +				{ 0 },
> +				{ 0 },
> +				{ 432000000, 594000000, 675000000, 727000000 }, },

Nit:
	Can you align clock and clock_rate wrap method,

	"gcc_hf_axi", "camnoc_axi", "cpas_ahb",

	{0}, { 300000000, 400000000 }, {0},

1st line have 3 clock at .clock,
clock rate also 3 clock_rate.

So reader can know corresponding rate quickly,

	for example, If I know rate of cpas_fast_ahb, reader can simple
locate by second row and second col.

Frank