[PATCH v5 06/11] phy: qualcomm: qmp-combo: Add v8 PCS-level drive level tables for Glymur

[Nabige Aala]

On 10/22/2026 4:10 PM, Konrad Dybcio wrote:
> On 10/1/26 11:34 AM, Nabige Aala wrote:
>> From: Ritesh Kumar <ritesh.kumar at oss.qualcomm.com>
>>
>> Add PCS-level drive level tables for the Glymur (V8) DP PHY:
>> - qmp_dp_v8_ln_drv_lvl_hbr3_hbr2: LN0/LN1_DRV_LVL settings for HBR3/HBR2
>> - qmp_dp_v8_ln_drv_lvl_hbr_rbr: LN0/LN1_DRV_LVL settings for HBR/RBR
>> - qmp_dp_v8_pre_emphasis_hbr_rbr: updated TX_EMP_POST1_LVL values for
>>   HBR/RBR
> [...]
>
>> +/* HBR3 & HBR2: DP2_LN0/LN1_DRV_LVL swing settings (PCS level) */
> These comments are a bit superfluous
Ack, I will drop the comment in the next revision.
>
> [...]
>
>> +	/* PCS-level drive level tables (v8 / Glymur) */
>> +	const u8 (*ln_drv_lvl_hbr_rbr)[4][4];
>> +	const u8 (*ln_drv_lvl_hbr3_hbr2)[4][4];
> Why can't we reuse the existing fields?

No other existing fields are matching these two tables. That's why I 
added a new field

Thanks,

Nabige

>
> Konrad