[PATCH v5 05/11] phy: qualcomm: qmp-combo: Add hardware-specific dp_aux_cfg2 and dp_phy_cfg1 fields

[Nabige Aala]

On 10/22/2026 4:04 PM, Konrad Dybcio wrote:
> On 10/1/26 11:34 AM, Nabige Aala wrote:
>> From: Ritesh Kumar <ritesh.kumar at oss.qualcomm.com>
>>
>> Add dp_aux_cfg2 and dp_phy_cfg1 fields to qmp_phy_cfg to allow
>> hardware-specific DP PHY register values to be specified per-platform
>> rather than hardcoded in the configure functions.
>>
>> Define named constants QSERDES_DP_PHY_AUX_CFG2_V456/V8 and
>> QSERDES_DP_PHY_CFG1_V456/V8 for better readability and maintainability.
>>
>> Populate the new fields in all existing DP PHY cfg structures:
>> - V456-based platforms (sar2130p, sc8180x, sc8280xp, x1e80100, sm8250,
>>    sm8350, sm8475, sm8550, sm8650, sm8750) use V456 constants
>> - Glymur (V8) uses V8 constants
>>
>> Signed-off-by: Ritesh Kumar <ritesh.kumar at oss.qualcomm.com>
>> Signed-off-by: Mahadevan P <mahadevan.p at oss.qualcomm.com>
>> Signed-off-by: Nabige Aala <nabige.aala at oss.qualcomm.com>
>> ---
>>   drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 37 ++++++++++++++++++++++++++++++-
>>   1 file changed, 36 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
>> index 646e97a52886..ebe2e6136f7a 100644
>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
>> @@ -2486,6 +2486,14 @@ static const struct qmp_combo_lane_mapping dp_data_lanes[] = {
>>   
>>   struct qmp_combo;
>>   
>> +/* DP PHY AUX_CFG2 register values for different hardware versions */
>> +#define QSERDES_DP_PHY_AUX_CFG2_V456		0xa4
>> +#define QSERDES_DP_PHY_AUX_CFG2_V8		0x06
> The doc says this should be 0x16 for flipped typec

Thank you for the review, Konrad.

After checking the hardware documentation more carefully, AUX_CFG2 
depend upon the swap_sel, which does not indicate the Type-C 
orientation. Its value depends on the SoC hardware configuration — 
specifically how the AUX lines are physically wired on the board.

So tying AUX_CFG2 to TYPEC_ORIENTATION_REVERSE would be incorrect.

I also tested the approach you suggested, where different AUX_CFG2 
values are programmed based on the cable orientation. However, with that 
change, link training fails consistently.


Thanks,

Nabige

>
>> +/* DP PHY CFG_1 register values for different hardware versions */
>> +#define QSERDES_DP_PHY_CFG1_V456		0x0f
>> +#define QSERDES_DP_PHY_CFG1_V8			0x2f
> And this should reportedly be 0x13/0x53 for normal/flipped
>
> Konrad