[PATCH 7/7] media: qcom: camss: Add Waipio CAMSS support
Vladimir Zapolskiy
vz at kernel.org
Fri Oct 23 09:30:57 PDT 2026
Add support of the camera subsystem (CAMSS) found on Qualcomm Waipio SoC.
The CAMSS IP on Waipio contains:
* three CSID and two CSID lite, which are supported by CSID 680,
* three VFE and two VFE lite blocks, which are supported by VFE 680,
* three CSI test pattern generators, which are supported by TPG Gen1.
Qualcomm Waipio CSIPHYs are supported by the CSI2 PHY driver only.
Signed-off-by: Vladimir Zapolskiy <vz at kernel.org>
---
drivers/media/platform/qcom/camss/camss-vfe.c | 2 +
drivers/media/platform/qcom/camss/camss.c | 236 ++++++++++++++++++
drivers/media/platform/qcom/camss/camss.h | 1 +
3 files changed, 239 insertions(+)
diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c b/drivers/media/platform/qcom/camss/camss-vfe.c
index 2680a9914765..f2aada991a0d 100644
--- a/drivers/media/platform/qcom/camss/camss-vfe.c
+++ b/drivers/media/platform/qcom/camss/camss-vfe.c
@@ -353,6 +353,7 @@ static u32 vfe_src_pad_code(struct vfe_line *line, u32 sink_code,
case CAMSS_8550:
case CAMSS_8650:
case CAMSS_8775P:
+ case CAMSS_WAIPIO:
case CAMSS_X1E80100:
switch (sink_code) {
case MEDIA_BUS_FMT_YUYV8_1X16:
@@ -2013,6 +2014,7 @@ static int vfe_bpl_align_rdi(struct vfe_device *vfe)
case CAMSS_8550:
case CAMSS_8650:
case CAMSS_8775P:
+ case CAMSS_WAIPIO:
case CAMSS_X1E80100:
ret = 16;
break;
diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
index b0d60e70e4bb..efb8f9cc983c 100644
--- a/drivers/media/platform/qcom/camss/camss.c
+++ b/drivers/media/platform/qcom/camss/camss.c
@@ -2967,6 +2967,226 @@ static const struct resources_icc icc_res_sc8280xp[] = {
},
};
+static const struct camss_subdev_resources csid_res_waipio[] = {
+ /* CSID0 */
+ {
+ .regulators = {},
+ .clock = { "cpas_ahb", "csid", "csiphy_rx" },
+ .clock_rate = { { 0 },
+ { 480000000 },
+ { 400000000 }, },
+ .reg = { "csid0" },
+ .interrupt = { "csid0" },
+ .csid = {
+ .hw_ops = &csid_ops_680,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .formats = &csid_formats_gen2,
+ },
+ },
+ /* CSID1 */
+ {
+ .regulators = {},
+ .clock = { "cpas_ahb", "csid", "csiphy_rx" },
+ .clock_rate = { { 0 },
+ { 480000000 },
+ { 400000000 }, },
+ .reg = { "csid1" },
+ .interrupt = { "csid1" },
+ .csid = {
+ .hw_ops = &csid_ops_680,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .formats = &csid_formats_gen2,
+ },
+ },
+ /* CSID2 */
+ {
+ .regulators = {},
+ .clock = { "cpas_ahb", "csid", "csiphy_rx" },
+ .clock_rate = { { 0 },
+ { 480000000 },
+ { 400000000 }, },
+ .reg = { "csid2" },
+ .interrupt = { "csid2" },
+ .csid = {
+ .hw_ops = &csid_ops_680,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .formats = &csid_formats_gen2,
+ },
+ },
+ /* CSID_LITE0 */
+ {
+ .regulators = {},
+ .clock = { "cpas_ahb", "vfe_lite_csid", "vfe_lite_cphy_rx",
+ "csiphy_rx" },
+ .clock_rate = { { 0 },
+ { 480000000 },
+ { 400000000 },
+ { 400000000 }, },
+ .reg = { "csid_lite0" },
+ .interrupt = { "csid_lite0" },
+ .csid = {
+ .is_lite = true,
+ .hw_ops = &csid_ops_680,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .formats = &csid_formats_gen2,
+ },
+ },
+ /* CSID_LITE1 */
+ {
+ .regulators = {},
+ .clock = { "cpas_ahb", "vfe_lite_csid", "vfe_lite_cphy_rx",
+ "csiphy_rx" },
+ .clock_rate = { { 0 },
+ { 480000000 },
+ { 400000000 },
+ { 400000000 }, },
+ .reg = { "csid_lite1" },
+ .interrupt = { "csid_lite1" },
+ .csid = {
+ .is_lite = true,
+ .hw_ops = &csid_ops_680,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .formats = &csid_formats_gen2,
+ },
+ },
+};
+
+static const struct camss_subdev_resources vfe_res_waipio[] = {
+ /* IFE0 */
+ {
+ .regulators = {},
+ .clock = { "gcc_hf_axi", "camnoc_axi", "cpas_ahb",
+ "core_ahb", "cpas_fast_ahb", "cpas_vfe0",
+ "vfe0_fast_ahb", "vfe0" },
+ .clock_rate = { { 0 },
+ { 300000000, 400000000 },
+ { 0 },
+ { 0 },
+ { 0 },
+ { 0 },
+ { 0 },
+ { 432000000, 594000000, 675000000, 727000000 }, },
+ .reg = { "vfe0" },
+ .interrupt = { "vfe0" },
+ .vfe = {
+ .line_num = 4,
+ .pd_name = "ife0",
+ .hw_ops = &vfe_ops_680,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845,
+ },
+ },
+ /* IFE1 */
+ {
+ .regulators = {},
+ .clock = { "gcc_hf_axi", "camnoc_axi", "cpas_ahb",
+ "core_ahb", "cpas_fast_ahb", "cpas_vfe1",
+ "vfe1_fast_ahb", "vfe1" },
+ .clock_rate = { { 0 },
+ { 300000000, 400000000 },
+ { 0 },
+ { 0 },
+ { 0 },
+ { 0 },
+ { 0 },
+ { 432000000, 594000000, 675000000, 727000000 }, },
+ .reg = { "vfe1" },
+ .interrupt = { "vfe1" },
+ .vfe = {
+ .line_num = 4,
+ .pd_name = "ife1",
+ .hw_ops = &vfe_ops_680,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845,
+ },
+ },
+ /* IFE2 */
+ {
+ .regulators = {},
+ .clock = { "gcc_hf_axi", "camnoc_axi", "cpas_ahb",
+ "core_ahb", "cpas_fast_ahb", "cpas_vfe2",
+ "vfe2_fast_ahb", "vfe2" },
+ .clock_rate = { { 0 },
+ { 300000000, 400000000 },
+ { 0 },
+ { 0 },
+ { 0 },
+ { 0 },
+ { 0 },
+ { 432000000, 594000000, 675000000, 727000000 }, },
+ .reg = { "vfe2" },
+ .interrupt = { "vfe2" },
+ .vfe = {
+ .line_num = 4,
+ .pd_name = "ife2",
+ .hw_ops = &vfe_ops_680,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845,
+ },
+ },
+ /* IFE_LITE_0 */
+ {
+ .regulators = {},
+ .clock = { "gcc_hf_axi", "camnoc_axi", "cpas_ahb",
+ "core_ahb", "cpas_fast_ahb", "cpas_vfe_lite",
+ "vfe_lite_ahb", "vfe_lite" },
+ .clock_rate = { { 0 },
+ { 300000000, 400000000 },
+ { 0 },
+ { 0 },
+ { 0 },
+ { 400000000, 480000000 },
+ { 0 },
+ { 400000000, 480000000 }, },
+ .reg = { "vfe_lite0" },
+ .interrupt = { "vfe_lite0" },
+ .vfe = {
+ .is_lite = true,
+ .line_num = 4,
+ .hw_ops = &vfe_ops_680,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845,
+ },
+ },
+ /* IFE_LITE_1 */
+ {
+ .regulators = {},
+ .clock = { "gcc_hf_axi", "camnoc_axi", "cpas_ahb",
+ "core_ahb", "cpas_fast_ahb", "cpas_vfe_lite",
+ "vfe_lite_ahb", "vfe_lite" },
+ .clock_rate = { { 0 },
+ { 300000000, 400000000 },
+ { 0 },
+ { 0 },
+ { 0 },
+ { 400000000, 480000000 },
+ { 0 },
+ { 400000000, 480000000 }, },
+ .reg = { "vfe_lite1" },
+ .interrupt = { "vfe_lite1" },
+ .vfe = {
+ .is_lite = true,
+ .line_num = 4,
+ .hw_ops = &vfe_ops_680,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845,
+ },
+ },
+};
+
+static const struct resources_icc icc_res_waipio[] = {
+ {
+ .name = "ahb",
+ .icc_bw_tbl.avg = 150000,
+ .icc_bw_tbl.peak = 300000,
+ },
+ {
+ .name = "hf_mnoc",
+ .icc_bw_tbl.avg = 2097152,
+ .icc_bw_tbl.peak = 2097152,
+ },
+};
+
static const struct camss_subdev_resources csiphy_res_8550[] = {
/* CSIPHY0 */
{
@@ -5769,6 +5989,21 @@ static const struct camss_resources sc7280_resources = {
.vfe_num = ARRAY_SIZE(vfe_res_7280),
};
+static const struct camss_resources waipio_resources = {
+ .version = CAMSS_WAIPIO,
+ .pd_name = "top",
+ .tpg_res = tpg_res_8775p,
+ .csid_res = csid_res_waipio,
+ .vfe_res = vfe_res_waipio,
+ .csid_wrapper_res = &csid_wrapper_res_sm8550,
+ .icc_res = icc_res_waipio,
+ .icc_path_num = ARRAY_SIZE(icc_res_waipio),
+ .csiphy_num = 6,
+ .tpg_num = ARRAY_SIZE(tpg_res_8775p),
+ .csid_num = ARRAY_SIZE(csid_res_waipio),
+ .vfe_num = ARRAY_SIZE(vfe_res_waipio),
+};
+
static const struct camss_resources sm8550_resources = {
.version = CAMSS_8550,
.pd_name = "top",
@@ -5831,6 +6066,7 @@ static const struct of_device_id camss_dt_match[] = {
{ .compatible = "qcom,sm8250-camss", .data = &sm8250_resources },
{ .compatible = "qcom,sm8550-camss", .data = &sm8550_resources },
{ .compatible = "qcom,sm8650-camss", .data = &sm8650_resources },
+ { .compatible = "qcom,waipio-camss", .data = &waipio_resources },
{ .compatible = "qcom,x1e80100-camss", .data = &x1e80100_resources },
{ .compatible = "qcom,glymur-camss", .data = &x1e80100_resources },
{ }
diff --git a/drivers/media/platform/qcom/camss/camss.h b/drivers/media/platform/qcom/camss/camss.h
index 7dc2fd9f03e0..b62f555bd0f6 100644
--- a/drivers/media/platform/qcom/camss/camss.h
+++ b/drivers/media/platform/qcom/camss/camss.h
@@ -96,6 +96,7 @@ enum camss_version {
CAMSS_8550,
CAMSS_8650,
CAMSS_8775P,
+ CAMSS_WAIPIO,
CAMSS_X1E80100,
};
--
2.53.0
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