[PATCH v4 5/5] phy: qcom-qmp-ufs: Add Glymur support

[Manivannan Sadhasivam]

On 2026-10-09 16:05 +0530, Pradeep P V K wrote:
> Add the init sequence tables and config for the UFS QMP phy found in
> the Glymur SoC.
> 
> Similar to SM8750, the QSERDES RX and TX register offsets for
> glymur SoC follow the v7 register layout, while the remaining
> (PCS, MPHY base) register offsets follow v6 layout. Update the
> register layouts accordingly.
> 
> Reviewed-by: Abel Vesa <abel.vesa at oss.qualcomm.com>
> Acked-by: Konrad Dybcio <konrad.dybcio at oss.qualcomm.com>
> Signed-off-by: Pradeep P V K <pradeep.pragallapati at oss.qualcomm.com>

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam at oss.qualcomm.com>

- Mani