[PATCH RFC v3 03/12] dt-bindings: PCI: nxp,s32g-pcie: Fix SerDes PHY phandle in example

[Jan Petrous]

On Mon, Oct 12, 2026 at 01:43:05PM -0500, Frank Li wrote:
> On Sat, Sep 19, 2026 at 08:54:31AM +0200, Jan Petrous via B4 Relay wrote:
> > [You don't often get email from devnull+jan.petrous.oss.nxp.com at kernel.org. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
> >
> > From: "Jan Petrous (OSS)" <jan.petrous at oss.nxp.com>
> >
> > The example references the SerDes PHY as
> >
> >   phys = <&serdes0 PHY_TYPE_PCIE 0 0>;
> >
> > i.e. the SerDes node itself with three PHY cells. That does not match
> > the SerDes binding: the per-lane child node is the generic PHY
> > provider and carries '#phy-cells = <0>', while the SerDes node itself
> > has no '#phy-cells' at all.
> >
> > Point the example at the PCIe lane child instead, which is also what
> > the S32G3 board device trees use. The dt-bindings/phy/phy.h include is
> > dropped along with the now-unused PHY_TYPE_PCIE constant.
> >
> > The schema itself is unchanged; 'phys: maxItems: 1' already describes
> > the corrected form.
> >
> > Signed-off-by: Jan Petrous (OSS) <jan.petrous at oss.nxp.com>
> > ---
> >  Documentation/devicetree/bindings/pci/nxp,s32g-pcie.yaml | 3 +--
> >  1 file changed, 1 insertion(+), 2 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/pci/nxp,s32g-pcie.yaml b/Documentation/devicetree/bindings/pci/nxp,s32g-pcie.yaml
> > index 66a050028278..29323e50bd8b 100644
> > --- a/Documentation/devicetree/bindings/pci/nxp,s32g-pcie.yaml
> > +++ b/Documentation/devicetree/bindings/pci/nxp,s32g-pcie.yaml
> > @@ -82,7 +82,6 @@ unevaluatedProperties: false
> >  examples:
> >    - |
> >      #include <dt-bindings/interrupt-controller/arm-gic.h>
> > -    #include <dt-bindings/phy/phy.h>
> >
> >      bus {
> >          #address-cells = <2>;
> > @@ -124,7 +123,7 @@ examples:
> >                  ranges;
> >
> >                  device_type = "pci";
> > -                phys = <&serdes0 PHY_TYPE_PCIE 0 0>;
> > +                phys = <&serdes0_pcie0>;
> 
> I don't think it fix somethings. The "serdes0" just a label, point to
> provider, which is not neccsary that "#phy-cells" is 0.
> 
> Examples just show need how many phys and don't care about phy provider's
> arguments
> 

The example validates either way, agreed. The three cells are the
'#phy-cells = <3>' of the downstream nxp,s32cc-serdes binding, which
was never posted upstream; patch 1 is the only SerDes binding for S32G
and has no three-cell provider. I would rather have the example match
it.

The form depends on the outcome of your patch 1 comment, so I will
keep this patch in sync with that. If you prefer the phys line
untouched, I can drop it and keep only the ranges fix v4 adds here.

BR.
/Jan