[PATCH 3/3] phy: phy-snps-eusb2: Enable AHB2PHY bus clock on Nord

[Bartosz Golaszewski]

On Thu, 8 Oct 2026 03:50:17 +0200, Shawn Guo
<shengchao.guo at oss.qualcomm.com> said:
> On Nord, the eUSB2 PHY registers sit behind the AHB2PHY_0 bridge, gated
> by NE_GCC_AHB2PHY_CLK. The Nord PHY currently matches the sm8550
> fallback, which only requests the "ref" clock, so the bridge clock is
> never enabled by the PHY. When nothing else holds it, e.g. on boards
> where only the USB20-only controller is in use, clk_disable_unused()
> gates the bridge and PHY init accesses go nowhere:
>
>   xhci-hcd xhci-hcd.2.auto: can't setup: -110
>
> Add Nord-specific match data that requests both "ref" and "bus" clocks,
> reusing the existing Qualcomm init sequence. The bus clock is enabled
> and disabled together with the ref clock in phy init/exit.
>
> Signed-off-by: Shawn Guo <shengchao.guo at oss.qualcomm.com>
> ---

Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski at oss.qualcomm.com>
Tested-by: Bartosz Golaszewski <bartosz.golaszewski at oss.qualcomm.com>