[PATCH v2 04/13] drm/msm/dpu: Add support for DPU 12.1 on Nord

[Dmitry Baryshkov]

On Mon, Oct 12, 2026 at 07:02:14PM +0530, Nabige Aala wrote:
> From: Mahadevan P <mahadevan.p at oss.qualcomm.com>
> 
> Add the DPU catalog entry for the Qualcomm Nord SoC (MDSS 12.1, DPU
> 1499A). Nord is DP-only with no DSI, and provides 8 DSPP blocks, 2
> writeback blocks, 8 interfaces and 2 DP controllers.
> 
> Extend enum dpu_intf with INTF_9 and INTF_10, which Nord is the first
> platform to use. The new entries are inserted before MDP_INTF1_TEAR_INTR
> and MDP_INTF2_TEAR_INTR in enum dpu_hw_intr_reg, preserving the
> contiguous MDP_INTF0_INTR..MDP_INTF10_INTR block that the
> MDP_INTFn_INTR() macro relies on for correct index arithmetic.
> 
> Corresponding register entries are added to dpu_intr_set_7xxx (required
> for Nord, which has core_major_ver = 12) and dpu_intr_set_13xx (for
> consistency and to avoid a latent bug on future 13xx-family SoCs that
> use INTF 9 or 10).

Which latent bug? Please split INTF_9 / INTF_10 handling to a separate
patch.

> 
> Assisted-by: LLM
> Signed-off-by: Mahadevan P <mahadevan.p at oss.qualcomm.com>
> Signed-off-by: Nabige Aala <nabige.aala at oss.qualcomm.com>
> ---
>  .../gpu/drm/msm/disp/dpu1/catalog/dpu_12_1_nord.h  | 544 +++++++++++++++++++++
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c     |   1 +
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h     |   1 +
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c  |  20 +
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h  |   2 +
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h        |   2 +
>  drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c            |   1 +
>  7 files changed, 571 insertions(+)
> 

-- 
With best wishes
Dmitry