[PATCH 2/4] PCI: qcom-ep: Move PHY init and drive PHY reset to align with HPG

[Manivannan Sadhasivam]

On Tue, Sep 15, 2026 at 11:04:22PM -0700, Qiang Yu wrote:
> HPG requires the GDSC to be powered up and all PHY/controller clocks
> enabled before the controller's core reset and the PHY's reset are toggled
> together as one atomic group, with PARF_DEVICE_TYPE set right after that
> reset group, same as the RC-mode change.
> 
> Move phy_init() ahead of the controller's own clock enable, and fold
> phy_reset() into the core reset assert/deassert. phy_power_on() keeps
> running afterwards. Also move the PARF_DEVICE_TYPE write out of
> qcom_pcie_perst_deassert() to right after the reset group, in
> qcom_pcie_enable_resources().
> 

Sashiko pointed out that PARF_DEVICE_TYPE change is not present in this patch.

- Mani

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