[PATCH v4 08/13] phy: qualcomm: qcom-uniphy-pcie-usb3-28lp: Add support for USB3 PHY on IPQ5018

[Manivannan Sadhasivam]

On Tue, Sep 08, 2026 at 01:41:01PM +0400, George Moussalem via B4 Relay wrote:
> From: George Moussalem <george.moussalem at outlook.com>
> 
> Add support for the USB3 PHY on IPQ5018 chipsets.
> 
> The PHY outputs a 250MHz PIPE clock routed to and gated by the GCC, so
> register a fixed rate clock. In addition, add the register/value pairs
> for the PHY initialization sequence.
> 
> The code to acquire clocks and resets is the same as for PCIe so no
> changes are needed. Add a USB3-specific helper function to acquire the
> required regulator and TCSR syscon for USB mux selection. The PCIe and
> USB3 pads are muxed so select USB3 mode in TCSR which needs to occur
> before the DWC3 USB3 controller resets. Otherwise, the SS link doesn't
> train and remains stuck in RX.Detect.
> 
> Add PHY ops for USB3 power on/off sequences to account for USB3-specific
> delay timings and enabling/disabling the PHY supply.
> 
> Rename the existing reset delay timings to describe they are for PCIe.
> Lastly, add the USB3 PHY type to the UNIPHY PHY type enum and remove the
> GEN2 and GEN3 PCIe types as the driver makes no distinction between the
> two which also makes it easier to distinguish between the PCIe and USB3
> PHYs.
> 
> Tested-by: Stanislaw Pal <kuncy7 at gmail.com>
> Signed-off-by: George Moussalem <george.moussalem at outlook.com>

LGTM! Just one minor nit below. With that fixed,

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam at oss.qualcomm.com>

> ---
>  .../phy/qualcomm/phy-qcom-uniphy-pcie-usb3-28lp.c  | 178 ++++++++++++++++++---
>  1 file changed, 159 insertions(+), 19 deletions(-)
> 

[...]

> +static inline int qcom_uniphy_usb3_get_resources(struct platform_device *pdev,
> +						 struct qcom_uniphy *phy)

Drop the 'inline' keyword please. Modern compilers will inline functions on
their own irrespective of this keyword.

- Mani

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