[PATCH 1/3] dt-bindings: phy: aspeed: Add ASPEED PCIe PHY

[Krzysztof Kozlowski]

On Thu, Oct 08, 2026 at 07:28:19PM +0800, Jacky Chou wrote:
> Introduce device-binding for ASPEED AST2600/2700 PCIe PHY.
> The PHY provides the physical layer used by the PCIe
> controller when operating in root complex mode.
> 
> Describe the compatible strings, register range, clocks and
> phy-cells value required by the PHY provider.
> 
> Signed-off-by: Jacky Chou <jacky_chou at aspeedtech.com>
> ---
>  .../bindings/phy/aspeed,ast2600-pcie-phy.yaml      | 49 ++++++++++++++++++++++
>  1 file changed, 49 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/phy/aspeed,ast2600-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/aspeed,ast2600-pcie-phy.yaml
> new file mode 100644
> index 000000000000..686b2e3d9457
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/aspeed,ast2600-pcie-phy.yaml

What? v9 here:
https://lore.kernel.org/all/20260115-upstream_pcie_rc-v9-1-d6c82a1556a7@aspeedtech.com/
from the same person, reviewed, but you ask us to do the same work
second time? Really?

Best regards,
Krzysztof