[PATCH v19 02/12] phy: qcom-mipi-csi2: Parametrise the common status register offset

[bod at kernel.org]

On 2026-10-08 00:14 -0700, Hangxiang Ma wrote:
> The CSI2 PHY common status registers are not at a fixed offset from the
> common register block across SoCs: x1e80100 uses 0xb0 while other 3PH
> v2.4.0 parts differ.
> 
> Replace the hard-coded 0xb0 in CSIPHY_3PH_CMN_CSI_COMMON_STATUSn() with
> a per-SoC common_status_offset field in struct mipi_csi2phy_device_regs,
> initialising x1e80100 to 0xb0 so behaviour is unchanged. This is a
> no-functional-change preparation for describing other SoC offsets.
> 
> Signed-off-by: Hangxiang Ma <hangxiang.ma at oss.qualcomm.com>
>  	csi2phy->hw_version |= (tmp << 8) & 0xFF00;

Reviewed-by: Bryan O'Donoghue <bod at kernel.org>

-- 
Bryan O'Donoghue <bod at kernel.org>