[PATCH v19 10/12] arm64: dts: qcom: kaanapali: Add CAMSS and CSIPHY block definitions

[sashiko-bot at kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] dts: missing SoC-internal OF graph links between camss and standalone csiphy nodes
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commit a63685b077e80fcbb61d58b04d437addeb277a93
Author: Hangxiang Ma <hangxiang.ma at oss.qualcomm.com>

arm64: dts: qcom: kaanapali: Add CAMSS and CSIPHY block definitions

This commit describes the CAMSS and CSIPHY blocks on the Kaanapali SoC.
It adds 6 CSIPHYs, 3 TPGs, 3 CSIDs, 2 CSID Lites, 3 VFEs, and 2 VFE Lites
to enable camera pipelines on board device trees.

> diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
> index e48a179d07220..7e5106865e7ee 100644
> --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi
> +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi

[ ... ]

> @@ -3597,6 +3598,307 @@ usb_dp_qmpphy_dp_in: endpoint {
>  			};
>  		};
>  
> +		camss: isp at 9253000 {
> +			compatible = "qcom,kaanapali-camss";

[ ... ]

> +			status = "disabled";
> +
> +			ports {
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +
> +				port at 0 {
> +					reg = <0>;
> +				};
> +
> +				port at 1 {
> +					reg = <1>;
> +				};

[Severity: High]
Will the CAMSS driver be able to find the CSIPHY devices with these empty
port definitions?

The CAMSS driver (msm_csiphy_subdev_init in camss-csiphy.c) discovers its
PHYs by traversing the OF graph using of_graph_get_endpoint_by_regs on the
camss node's ports, following it to the remote endpoint's parent, and calling
devm_phy_get_by_of_node.

Because these ports lack endpoint definitions linking back to the CSIPHY
outputs, the lookup will return NULL and silently skip PHY initialization.
This leaves the phy uninitialized and prevents the PHYs from powering on
during streaming.

[ ... ]

> +			};
> +		};
> +
> +		csiphy0: phy at 9523000 {
> +			compatible = "qcom,kaanapali-csi2-phy";
> +			reg = <0x0 0x09523000 0x0 0x2000>;
> +
> +			clocks = <&camcc CAM_CC_CSIPHY0_CLK>,

[Severity: High]
Does this standalone csiphy0 node also need a ports structure to define its
CAMSS output endpoint?

Without a ports definition in the csiphy nodes, the OF graph traversal from
the camss node cannot resolve the remote endpoint, breaking the internal
SoC routing required to initialize the PHYs.

Since these are hardwired SoC-internal connections between the PHY output
and the CAMSS input, shouldn't they be defined here in the .dtsi rather
than forcing downstream board .dts files to manually construct the internal
SoC routing?

[ ... ]

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Sashiko AI review · https://sashiko.dev/#/patchset/20261008-kaanapali-camss-v19-0-b2c583ef50e0@oss.qualcomm.com?part=10