[PATCH v4 5/6] phy: qcom: snps-femto-v2: Move PHY init registers to config tables

[Dmitry Baryshkov]

On Mon, Oct 05, 2026 at 12:06:30PM +0530, Varadarajan Narayanan wrote:
> The driver currently programs the common PHY register sequence directly in
> qcom_snps_hsphy_init(), with the fixed register writes split around the
> override parameter handling. This makes it hard to support SoCs that need a
> different sequence or different values.
> 
> Move the fixed pre- and post-override register programming into per-
> compatible configuration tables, and keep the 7 nm override parameters in
> the same match-data structure. This allows the driver to share the common
> sequence while adding SoC-specific sequences for future platforms such as
> IPQ9650.
> 
> Signed-off-by: Varadarajan Narayanan <varadarajan.narayanan at oss.qualcomm.com>
> ---
>  drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c | 124 ++++++++++++++++----------
>  1 file changed, 78 insertions(+), 46 deletions(-)
> 
> -	qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL1,
> -					VBUSVLDEXT0, VBUSVLDEXT0);
> +	for (tmp = data->pre_tuning, i = 0; i < data->num_pre_tuning; i++, tmp++)
> +		qcom_snps_hsphy_write_mask(hsphy->base, tmp->offset, tmp->mask, tmp->val);

for (i = 0; i < data->num_pre_tuning; i++)
	qcom_snps_hsphy_write_mask(hsphy->base,
				   data->pre_tuning[i].offset,
				   data->pre_tuning[i].mask,
				   data->pre_tuning[i].val);

>  
>  	for (i = 0; i < ARRAY_SIZE(hsphy->update_seq_cfg); i++) {
>  		if (hsphy->update_seq_cfg[i].need_update)
> -	qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_CFG0,
> -					UTMI_PHY_CMN_CTRL_OVERRIDE_EN, 0);
> +	for (tmp = data->post_tuning, i = 0; i < data->num_post_tuning; i++, tmp++)
> +		qcom_snps_hsphy_write_mask(hsphy->base, tmp->offset, tmp->mask, tmp->val);

And here too.

>  
>  	hsphy->phy_initialized = true;
>  

-- 
With best wishes
Dmitry