[PATCH v2] phy: qcom: qmp-combo: Leave the USB PCS alone in DP-only mode

[Joonhoe Kim]

On 11/2/26 10:32 PM, Konrad Dybcio wrote:
> On 10/23/26 2:35 PM, Joonhoe Kim wrote:
[...]
>> -	ret = qmp_combo_usb_power_on(phy);
>> -	if (ret) {
>> -		qmp_combo_com_exit(qmp, false);
>> -		return ret;
>> +	if (qmp->qmpphy_mode != QMPPHY_MODE_DP_ONLY) {
>> +		ret = qmp_combo_usb_power_on(phy);
[...]
> The USB sub-block provides the PIPE clock to the DWC3 controller.
> If we somehow enter DP altmode before DWC3 gets to probe, or if for
> any reason we need to access that controller (maybe debugfs reads),
> I think this will fail.

Right, there is no PIPE clock then. But there is none without this
patch either.

In DP-only mode, qmp_combo_usb_power_on() writes the USB tables over
the lanes DP is using. Here it timed out waiting for PHYSTATUS when
resuming in that mode, so phy_init() fails.

DP-only mode is usually entered after DWC3 has probed. The mux then
powers the USB PCS down under the running controller. So accessing the
controller in that state already has no PIPE clock today.

With this patch, the probe-after-DP case ends up in the same state
instead of failing in phy_init().

The missing PIPE clock does break things on Kaanapali: starting the
host in DP-only mode fails ("Host halt failed, -110"). I've sent a
dwc3-qcom series for this [1]. It switches the controller to the UTMI
clock in DP-only modes, like "qcom,select-utmi-as-pipe-clk" does
statically. It also makes the controller a mode switch, so
pmic_glink_altmode cannot set the mux before dwc3-qcom has probed.

[1] https://lore.kernel.org/all/20261102215121.738-1-26rote@gmail.com/

Thanks,
Joonhoe Kim