[PATCH v23 12/15] arm64: dts: qcom: kaanapali: Add CAMSS and CSIPHY block definitions

[Hangxiang Ma]

On 10/31/2026 7:46 PM, Vladimir Zapolskiy wrote:
> On 10/28/26 17:20, Hangxiang Ma wrote:
>> Describe the CAMSS and CSIPHY blocks on Kaanapali so that camera 
>> pipelines
>> can be enabled by board device trees.
>>
>> The camera subsystem contains:
>> - 6 x CSIPHY (CSI Physical Layer)
>> - 3 x TPG (Test Pattern Generator)
>> - 3 x CSID (CSI Decoder)
>> - 2 x CSID Lite
>> - 3 x VFE (Video Front End), 5 RDI per VFE
>> - 2 x VFE Lite, 4 RDI per VFE Lite
>>
>> Reviewed-by: Konrad Dybcio <konrad.dybcio at oss.qualcomm.com>
>> Signed-off-by: Hangxiang Ma <hangxiang.ma at oss.qualcomm.com>
>> ---
>>   arch/arm64/boot/dts/qcom/kaanapali.dtsi | 401 ++++++++++++++++++++++ 
>> ++++++++++
>>   1 file changed, 401 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/ 
>> boot/dts/qcom/kaanapali.dtsi
>> index e48a179d0722..0c8fd7da55b7 100644
>> --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
>> @@ -20,6 +20,7 @@
>>   #include <dt-bindings/interconnect/qcom,kaanapali-rpmh.h>
>>   #include <dt-bindings/interrupt-controller/arm-gic.h>
>>   #include <dt-bindings/mailbox/qcom-ipcc.h>
>> +#include <dt-bindings/phy/phy.h>
>>   #include <dt-bindings/phy/phy-qcom-qmp.h>
>>   #include <dt-bindings/power/qcom-rpmpd.h>
>>   #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
>> @@ -3597,6 +3598,384 @@ usb_dp_qmpphy_dp_in: endpoint {
>>               };
>>           };
>> +        camss: isp at 900b000 {
>> +            compatible = "qcom,kaanapali-camss";
>> +
>> +            reg = <0x0 0x0900b000 0x0 0x1000>,
>> +                  <0x0 0x09253000 0x0 0x5e80>,
>> +                  <0x0 0x09263000 0x0 0x5e80>,
>> +                  <0x0 0x09273000 0x0 0x5e80>,
>> +                  <0x0 0x092d3000 0x0 0x3880>,
>> +                  <0x0 0x092e7000 0x0 0x3880>,
>> +                  <0x0 0x093fd000 0x0 0x400>,
>> +                  <0x0 0x093fe000 0x0 0x400>,
>> +                  <0x0 0x093ff000 0x0 0x400>,
>> +                  <0x0 0x09151000 0x0 0x20000>,
>> +                  <0x0 0x09171000 0x0 0x20000>,
>> +                  <0x0 0x09191000 0x0 0x20000>,
>> +                  <0x0 0x092dc000 0x0 0x1300>,
>> +                  <0x0 0x092f0000 0x0 0x1300>;
>> +            reg-names = "top",
>> +                    "csid0",
>> +                    "csid1",
>> +                    "csid2",
>> +                    "csid_lite0",
>> +                    "csid_lite1",
>> +                    "csitpg0",
>> +                    "csitpg1",
>> +                    "csitpg2",
> 
> These I/O regions should be named "tpgX".
>

ACK

>> +                    "vfe0",
>> +                    "vfe1",
>> +                    "vfe2",
>> +                    "vfe_lite0",
>> +                    "vfe_lite1";
>> +
>> +            clocks = <&camcc CAM_CC_CAMNOC_NRT_AXI_CLK>,
>> +                 <&camcc CAM_CC_CAMNOC_RT_AXI_CLK>,
>> +                 <&camcc CAM_CC_CAM_TOP_AHB_CLK>,
>> +                 <&camcc CAM_CC_CAM_TOP_FAST_AHB_CLK>,
>> +                 <&camcc CAM_CC_CAMNOC_RT_TFE_0_MAIN_CLK>,
>> +                 <&camcc CAM_CC_CAMNOC_RT_TFE_1_MAIN_CLK>,
>> +                 <&camcc CAM_CC_CAMNOC_RT_TFE_2_MAIN_CLK>,
>> +                 <&camcc CAM_CC_CAMNOC_RT_IFE_LITE_CLK>,
>> +                 <&camcc CAM_CC_CSID_CLK>,
>> +                 <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>,
>> +                 <&gcc GCC_CAMERA_HF_AXI_CLK>,
>> +                 <&gcc GCC_CAMERA_SF_AXI_CLK>,
>> +                 <&camcc CAM_CC_TFE_0_MAIN_CLK>,
>> +                 <&camcc CAM_CC_TFE_0_MAIN_FAST_AHB_CLK>,
>> +                 <&camcc CAM_CC_TFE_1_MAIN_CLK>,
>> +                 <&camcc CAM_CC_TFE_1_MAIN_FAST_AHB_CLK>,
>> +                 <&camcc CAM_CC_TFE_2_MAIN_CLK>,
>> +                 <&camcc CAM_CC_TFE_2_MAIN_FAST_AHB_CLK>,
>> +                 <&camcc CAM_CC_IFE_LITE_CLK>,
>> +                 <&camcc CAM_CC_IFE_LITE_AHB_CLK>,
>> +                 <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
>> +                 <&camcc CAM_CC_IFE_LITE_CSID_CLK>,
>> +                 <&camcc CAM_CC_QDSS_DEBUG_XO_CLK>;
>> +            clock-names = "camnoc_nrt_axi",
>> +                      "camnoc_rt_axi",
>> +                      "cpas_ahb",
>> +                      "cpas_fast_ahb",
>> +                      "cpas_vfe0",
>> +                      "cpas_vfe1",
>> +                      "cpas_vfe2",
>> +                      "cpas_vfe_lite",
>> +                      "csid",
>> +                      "csid_csiphy_rx",
> 
> This clock should be named "csiphy_rx" like on sa8775p and a number
> of other platforms.
> 

ACK

>> +                      "gcc_axi_hf",
>> +                      "gcc_axi_sf",

Will remove this unused clock as well>> +                      "vfe0",
>> +                      "vfe0_fast_ahb",
>> +                      "vfe1",
>> +                      "vfe1_fast_ahb",
>> +                      "vfe2",
>> +                      "vfe2_fast_ahb",
>> +                      "vfe_lite",
>> +                      "vfe_lite_ahb",
>> +                      "vfe_lite_cphy_rx",
>> +                      "vfe_lite_csid",
>> +                      "qdss_debug_xo";


---
Best Regards,
Hangxiang