[PATCH v18 2/7] phy: rockchip: usbdp: Add reset hook support for dwc3

[Manivannan Sadhasivam]

On 2026-10-21 20:05 +0200, Sebastian Reichel wrote:
> When TCPM (Type-C Port Manager) triggers a orientation or mux
> change, the PHY needs to reset. This results in the PHY no longer
> providing a clock to the USB controller. If the USB controller
> registers are accessed without the clock, SErrors are generated.
> 
> This can be avoided by switching the clock provider for the USB
> controller. But after switching the clock, the USB PHY sometimes does
> not succeed to lock its "cmn ana lcpll" PLLs again. I suspect this is
> due to a clock glitch and after some debugging figured out that this
> can be avoided by disabling the USB controller's PIPE interface while
> the PHY reset is ongoing.
> 
> Implement an API that allows the USBDP to actively request a reset
> from DWC3 as a quirk.
> 
> Signed-off-by: Sebastian Reichel <sebastian.reichel at collabora.com>

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam at oss.qualcomm.com>

- Mani