[PATCH v4 1/2] phy: ti: pipe3: Fix clock resource leak on probe errors

[sashiko-bot at kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Clock reference leak in ti_pipe3_init() on PCIe error path.
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commit 26f79663d08d9c0cec90795a1b32d3e5e37b7841
Author: Hongling Zeng <zenghongling at kylinos.cn>

phy: ti: pipe3: Fix clock resource leak on probe errors

When devm_phy_create() or devm_of_phy_provider_register() fails,
the refclk that was enabled earlier is not disabled, causing a
resource leak.

Fix this by adding an error handling path to disable the clock
when these functions fail.

Fixes: 234738ea3390 ("phy: ti-pipe3: move clk initialization to a separate function")
Signed-off-by: Hongling Zeng <zenghongling at kylinos.cn>

> Fix this by adding an error handling path to disable the clock
> when these functions fail.

This isn't a bug in this patch, but while fixing clock leaks in this driver,
does ti_pipe3_init() also leak the clock references on the PCIe error path?

If regmap_update_bits() fails in ti_pipe3_init(), the function returns the
error without calling ti_pipe3_disable_clocks():

drivers/phy/ti/phy-ti-pipe3.c:ti_pipe3_init() {
	ti_pipe3_enable_clocks(phy);
	...
	if (phy->mode == PIPE3_MODE_PCIE) {
		if (!phy->pcs_syscon) {
			omap_control_pcie_pcs(phy->control_dev, 0x96);
			return 0;
		}

		val = 0x96 << OMAP_CTRL_PCIE_PCS_DELAY_COUNT_SHIFT;
		ret = regmap_update_bits(phy->pcs_syscon, phy->pcie_pcs_reg,
					 PCIE_PCS_MASK, val);
		return ret;
	}
	...
}

Because the initialization fails, the core PHY framework will not invoke the
.exit callback, potentially leaving the clocks permanently enabled.

Unlike the ti_pipe3_dpll_program() error path later in the same function
which correctly calls ti_pipe3_disable_clocks(phy), this PCIe error path
appears to miss the cleanup.

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Sashiko AI review · https://sashiko.dev/#/patchset/20260518021539.14890-1-zenghongling@kylinos.cn?part=1