[PATCH 0/6] phy: rockchip: samsung-hdptx: Clock fixes and API transition cleanups

[Cristian Ciocaltea]

Hi Vinod,

On 5/10/26 10:36 AM, Vinod Koul wrote:
> On 27-02-26, 22:48, Cristian Ciocaltea wrote:
>> This series provides a set of bug fixes and cleanups for the Rockchip
>> Samsung HDPTX PHY driver.
>>
>> The first part of the series (i.e. PATCH 1 & 2) addresses clock rate
>> calculation and synchronization issues.  Specifically, it fixes edge
>> cases where the PHY PLL is pre-programmed by an external component (like
>> a bootloader) or when changing the color depth (bpc) while keeping the
>> modeline constant.  Because the Common Clock Framework .set_rate()
>> callback might not be invoked if the pixel clock remains unchanged, this
>> previously led to out-of-sync states between CCF and the actual HDMI PHY
>> configuration.
>>
>> The second part focuses on code cleanups and modernizing the register
>> access.  Now that dw_hdmi_qp driver has fully switched to using
>> phy_configure(), we can drop the deprecated TMDS rate setup workarounds
>> and the restrict_rate_change flag logic.  Finally, it refactors the
>> driver to consistently use standard bitfield macros.
> 
> Sorry looks like I have missed to review this one.
> Can you please rebase on phy/fixes and send...

I've just verified and it applies cleanly on top of phy/fixes.
Do you still need a resend?

Regards,
Cristian