[PATCH 06/12] riscv: dts: thead: add device nodes for USB

[Icenowy Zheng]

The TH1520 SoC contains a Synopsys DesignWare Cores SuperSpeed USB3.0
Dual Role Device controller in addition to a USB2+USB3 combo PHY based
on Synopsys USB3.0 FemtoPHY.

Add device tree nodes for them. The USB controller is quite generic, new
and properly configured during silicon design, but the PHY is a little
quirky.

Signed-off-by: Icenowy Zheng <zhengxingda at iscas.ac.cn>
---
 arch/riscv/boot/dts/thead/th1520.dtsi | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
index c9930e63bbe93..a6a3e114d0d2f 100644
--- a/arch/riscv/boot/dts/thead/th1520.dtsi
+++ b/arch/riscv/boot/dts/thead/th1520.dtsi
@@ -316,6 +316,20 @@ uart0: serial at ffe7014000 {
 			status = "disabled";
 		};
 
+		usb: usb at ffe7040000 {
+			compatible = "snps,dwc3";
+			reg = <0xff 0xe7040000 0x0 0x10000>;
+			interrupts = <68 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk_misc CLK_USB>,
+				 <&clk_misc CLK_USB_CTL_REF>,
+				 <&clk_misc CLK_USB_SUSPEND>;
+			clock-names = "bus_early", "ref", "suspend";
+			resets = <&rst_misc TH1520_RESET_ID_USB3_VCC>;
+			phys = <&usb_phy>;
+			phy-names = "usb3-phy";
+			status = "disabled";
+		};
+
 		gmac1: ethernet at ffe7060000 {
 			compatible = "thead,th1520-gmac", "snps,dwmac-3.70a";
 			reg = <0xff 0xe7060000 0x0 0x2000>, <0xff 0xec004000 0x0 0x1000>;
@@ -540,6 +554,19 @@ clk_misc: clock-controller at ffec02c100 {
 			#clock-cells = <1>;
 		};
 
+		usb_phy: phy at ffec030000 {
+			compatible = "thead,th1520-usb-phy";
+			reg = <0xff 0xec030000 0x0 0x10000>;
+			clocks = <&clk_misc CLK_USB>,
+				 <&clk_misc CLK_USB_PHY_REF>;
+			clock-names = "bus", "ref";
+			resets = <&rst_misc TH1520_RESET_ID_USB3_APB>,
+				 <&rst_misc TH1520_RESET_ID_USB3_PHY>;
+			reset-names = "bus", "phy";
+			#phy-cells = <0>;
+			status = "disabled";
+		};
+
 		rst_vp: reset-controller at ffecc30000 {
 			compatible = "thead,th1520-reset-vp";
 			reg = <0xff 0xecc30000 0x0 0x14>;
-- 
2.52.0