[PATCH v2] phy: cadence: Sierra: Do not modify register when getting parent clock

[Neil Armstrong]

On 3/6/26 11:23, Gregory CLEMENT wrote:
> The get_parent() callback for the PLL_CMNLC1 clock was incorrectly
> writing to the register while determining the parent clock index. This
> unintended register access forces the PHY back into training mode. If
> the PHY is already configured, this unexpected change prevents it from
> exiting training mode.
> 
> Remove the register write operation to ensure the PHY remains stable
> during the get_parent() callback.
> 
> Fixes: da08aab940092 ("phy: cadence: Sierra: Fix to get correct parent for mux clocks")
> Signed-off-by: Gregory CLEMENT <gregory.clement at bootlin.com>
> ---
> Changes in v2:
> 
> - Removed unused variable spotted by the 0-DAY CI Kernel Test Service:
>    https://lore.kernel.org/oe-kbuild-all/202603061235.hrl27Jvj-lkp@intel.com/
> - Link to v1: https://lore.kernel.org/r/20260305-fix_sierra_get_parent-v1-1-a7c18e9e6c58@bootlin.com
> ---
>   drivers/phy/cadence/phy-cadence-sierra.c | 11 ++---------
>   1 file changed, 2 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c
> index 92ab1a31646ae..dbeda7f01cbb2 100644
> --- a/drivers/phy/cadence/phy-cadence-sierra.c
> +++ b/drivers/phy/cadence/phy-cadence-sierra.c
> @@ -698,23 +698,16 @@ static const struct phy_ops noop_ops = {
>   static u8 cdns_sierra_pll_mux_get_parent(struct clk_hw *hw)
>   {
>   	struct cdns_sierra_pll_mux *mux = to_cdns_sierra_pll_mux(hw);
> -	struct regmap_field *plllc1en_field = mux->plllc1en_field;
> -	struct regmap_field *termen_field = mux->termen_field;
>   	struct regmap_field *field = mux->pfdclk_sel_preg;
>   	unsigned int val;
>   	int index;
>   
>   	regmap_field_read(field, &val);
>   
> -	if (strstr(clk_hw_get_name(hw), clk_names[CDNS_SIERRA_PLL_CMNLC1])) {
> +	if (strstr(clk_hw_get_name(hw), clk_names[CDNS_SIERRA_PLL_CMNLC1]))
>   		index = clk_mux_val_to_index(hw, cdns_sierra_pll_mux_table[CMN_PLLLC1], 0, val);
> -		if (index == 1) {
> -			regmap_field_write(plllc1en_field, 1);
> -			regmap_field_write(termen_field, 1);
> -		}
> -	} else {
> +	else
>   		index = clk_mux_val_to_index(hw, cdns_sierra_pll_mux_table[CMN_PLLLC], 0, val);
> -	}
>   
>   	return index;
>   }
> 
> ---
> base-commit: 11439c4635edd669ae435eec308f4ab8a0804808
> change-id: 20260305-fix_sierra_get_parent-9c8435cc65e7
> 
> Best regards,

Reviewed-by: Neil Armstrong <neil.armstrong at linaro.org>

Thanks,
Neil