[PATCH 7/9] arm64: dts: qcom: shikra: Add PCIe PHY and controller nodes
Sushrut Shree Trivedi
sushrut.trivedi at oss.qualcomm.com
Tue Jun 30 12:02:49 PDT 2026
Shikra supports single PCIe instance with 5GT/s x1 lane.
Add PCIe controller and PHY node for this single instance.
Signed-off-by: Sushrut Shree Trivedi <sushrut.trivedi at oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/shikra.dtsi | 154 +++++++++++++++++++++++++++++++++++
1 file changed, 154 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi
index e67fe047a683..74d51ba5bde3 100644
--- a/arch/arm64/boot/dts/qcom/shikra.dtsi
+++ b/arch/arm64/boot/dts/qcom/shikra.dtsi
@@ -998,6 +998,160 @@ tsens0: thermal-sensor at 4411000 {
#thermal-sensor-cells = <1>;
};
+ pcie: pcie at 45e8000 {
+ device_type = "pci";
+ compatible = "qcom,shikra-pcie";
+ reg = <0x0 0x045e8000 0x0 0x3000>,
+ <0x0 0x60000000 0x0 0xf1d>,
+ <0x0 0x60000f20 0x0 0xa8>,
+ <0x0 0x60001000 0x0 0x1000>,
+ <0x0 0x60100000 0x0 0x100000>,
+ <0x0 0x045eb000 0x0 0x1000>;
+ reg-names = "parf",
+ "dbi",
+ "elbi",
+ "atu",
+ "config",
+ "mhi";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
+ <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>,
+ <0x03000000 0x4 0x00000000 0x4 0x00000000 0x3 0x0000000>;
+ bus-range = <0x00 0xff>;
+
+ linux,pci-domain = <0>;
+ num-lanes = <1>;
+
+ interrupts = <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 492 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 493 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "msi0",
+ "msi1",
+ "msi2",
+ "msi3",
+ "msi4",
+ "msi5",
+ "msi6",
+ "msi7",
+ "global";
+
+ interrupt-map = <0 0 0 1 &intc 0 0 0 499 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &intc 0 0 0 500 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &intc 0 0 0 501 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &intc 0 0 0 502 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ #interrupt-cells = <1>;
+
+ clocks = <&gcc GCC_PCIE_AUX_CLK>,
+ <&gcc GCC_PCIE_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_SLV_AXI_CLK>,
+ <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>,
+ <&gcc GCC_DDRSS_MEMNOC_PCIE_SF_CLK>,
+ <&gcc GCC_PCIE_TILE_AXI_SYS_NOC_CLK>,
+ <&gcc GCC_QMIP_PCIE_CFG_AHB_CLK>;
+ clock-names = "aux",
+ "cfg",
+ "bus_master",
+ "bus_slave",
+ "slave_q2a",
+ "ddrss_memnoc_pcie",
+ "tile",
+ "qmip_pcie_ahb";
+
+ assigned-clocks = <&gcc GCC_PCIE_AUX_CLK>;
+ assigned-clock-rates = <19200000>;
+
+ interconnects = <&system_noc MASTER_PCIE2_0 RPM_ALWAYS_TAG
+ &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ACTIVE_TAG
+ &config_noc SLAVE_PCIE2_0 RPM_ACTIVE_TAG>;
+
+ interconnect-names = "pcie-mem",
+ "cpu-pcie";
+
+ iommu-map = <0x0 &apps_smmu 0x800 0x1>,
+ <0x100 &apps_smmu 0x801 0x1>;
+
+ resets = <&gcc GCC_PCIE_BCR>;
+ reset-names = "pci";
+
+ power-domains = <&gcc GCC_PCIE_GDSC>;
+
+ max-link-speed = <2>;
+
+ operating-points-v2 = <&pcie_opp_table>;
+
+ status = "disabled";
+
+ pcie_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ /* GEN 1 x1 */
+ opp-2500000 {
+ opp-hz = /bits/ 64 <2500000>;
+ required-opps = <&rpmpd_opp_nom>;
+ opp-peak-kBps = <250000 1>;
+ opp-level = <1>;
+ };
+
+ /* GEN 2 x1 */
+ opp-5000000 {
+ opp-hz = /bits/ 64 <5000000>;
+ required-opps = <&rpmpd_opp_nom>;
+ opp-peak-kBps = <500000 1>;
+ opp-level = <2>;
+ };
+ };
+
+ pcie_port0: pcie at 0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ bus-range = <0x01 0x8>;
+
+ phys = <&pcie_phy>;
+ };
+ };
+
+ pcie_phy: phy at 45ee000 {
+ compatible = "qcom,shikra-qmp-gen2x1-pcie-phy";
+ reg = <0x0 0x045ee000 0x0 0x1000>;
+
+ clocks = <&gcc GCC_PCIE_AUX_CLK>,
+ <&gcc GCC_PCIE_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_CLKREF_EN>,
+ <&gcc GCC_PCIE_RCHNG_PHY_CLK>,
+ <&gcc GCC_PCIE_PIPE_CLK>;
+ clock-names = "aux",
+ "cfg_ahb",
+ "ref",
+ "refgen",
+ "pipe";
+
+ resets = <&gcc GCC_PCIE_PHY_BCR>;
+ reset-names = "phy";
+
+ assigned-clocks = <&gcc GCC_PCIE_RCHNG_PHY_CLK>;
+ assigned-clock-rates = <100000000>;
+
+ #clock-cells = <0>;
+ clock-output-names = "pcie_pipe_clk";
+
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
rpm_msg_ram: sram at 45f0000 {
compatible = "qcom,rpm-msg-ram", "mmio-sram";
reg = <0x0 0x045f0000 0x0 0x7000>;
--
2.43.0
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