[PATCH] phy: starfive: jh7110-dphy: fail init when the PLL does not lock

[sashiko-bot at kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] Failed PLL lock leaves the hardware out of reset, preventing clean initialization retries.
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commit 2ff03101ec29d4c2e1b0317fa73877af8894c09e
Author: Pengpeng Hou <pengpeng at iscas.ac.cn>

phy: starfive: jh7110-dphy: fail init when the PLL does not lock
    
This commit updates stf_dphy_hw_reset() to return a timeout error instead
of just logging it when the PHY PLL fails to lock. It also propagates this
error up through the initialization and exit paths so the driver can properly
fail when the lock condition is not met.

> diff --git a/drivers/phy/starfive/phy-jh7110-dphy-tx.c b/drivers/phy/starfive/phy-jh7110-dphy-tx.c
> --- a/drivers/phy/starfive/phy-jh7110-dphy-tx.c
> +++ b/drivers/phy/starfive/phy-jh7110-dphy-tx.c

[ ... ]

> @@ -224,8 +224,12 @@ static void stf_dphy_hw_reset(struct stf_dphy *dphy, int assert)
>  					       !(FIELD_GET(STF_DPHY_RGS_CDTX_PLL_UNLOCK, status)),
>  					       STF_DPHY_HW_DELAY_US, STF_DPHY_HW_TIMEOUT_US);
>  		if (rc)
> -			dev_err(dphy->dev, "MIPI dphy-tx # PLL Locked\n");
> +			dev_err(dphy->dev, "MIPI dphy-tx PLL failed to lock\n");
> +
> +		return rc;
>  	}

[Severity: Medium]
When stf_dphy_hw_reset() is called with assert set to 1, it writes 1 to the
STF_DPHY_RESETB bit to bring the PHY out of reset. If the PLL lock times out,
the function now returns an error early without reverting the register to 0.

Since phy_init() fails, phy_exit() won't be called to clean up. Does this
leave the hardware permanently out of reset in a dirty state? If the hardware
requires a 0-to-1 reset transition to attempt locking again, will subsequent
initialization retries automatically fail because the hardware was never put
back into reset?

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Sashiko AI review · https://sashiko.dev/#/patchset/20260624143911.58472-1-pengpeng@iscas.ac.cn?part=1